Spartan® Family FPGAs

[bassman59]

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alexgiul wrote:

Hi Sanjaac,

could you explain me what I see (also you) during the simulation of ddr core?

#    Time: 335105 ns  Iteration: 3  Instance: /video_streamer_tb/i0/u_4/top_00/controller0
# At time 335200.000 ns ACT  : Bank = 0, Row = 0000
# At time 335230.000 ns WRITE: Bank = 0, Col = 000
# At time 335245.000 ns WRITE: Bank = 0, Row = 0000, Col = 000, Data = 7c00
# At time 335250.000 ns WRITE: Bank = 0, Row = 0000, Col = 001, Data = 7c00

# At time 335250.000 ns WRITE: Bank = 0, Col = 004
# At time 335255.000 ns WRITE: Bank = 0, Row = 0000, Col = 002, Data = 7c00
# At time 335260.000 ns WRITE: Bank = 0, Row = 0000, Col = 003, Data = 7c00
# At time 335265.000 ns WRITE: Bank = 0, Row = 0000, Col = 004, Data = 7c00
# At time 335270.000 ns WRITE: Bank = 0, Row = 0000, Col = 005, Data = 7c00

# At time 335270.000 ns WRITE: Bank = 0, Col = 008
# At time 335275.000 ns WRITE: Bank = 0, Row = 0000, Col = 006, Data = 7c00

Why the first write cmd has 2 col addres and the second (004) four?

I'm a little confused...

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Looks like his test bench is simply doing a burst of two writes, followed by a burst of four. There is nothing particularly odd about this.

-a

[sanjaac]

Hi bassman59, Alex.

As bassman said, there is nothing special into it. You can just continue working with the code and core.

Good luck.

[alexgiul]

Hi bassman59, Sanjaac,

probably I post the question in uncorrect manner: I write code to obtain the waveforms of figure 7-9 page 254 of ug086.pdf.

In the note of figure, it's written:  DDR SDRAM Write Burst, Burst Lengths of Four and Two Bursts , so why the first write is 2 burst and second and other no?

According to the above figure, I have to increment the column counter , now I add 4 every iteration to column counter, but I'm not sure if it's right

[sanjaac]

Hi guys,

I will re-copy here were the ACTUAL writes are, for you to see it very clearly:

# At time 335245.000 ns WRITE: Bank = 0, Row = 0000, Col = 000, Data = 7c00
# At time 335250.000 ns WRITE: Bank = 0, Row = 0000, Col = 001, Data = 7c00

# At time 335255.000 ns WRITE: Bank = 0, Row = 0000, Col = 002, Data = 7c00
# At time 335260.000 ns WRITE: Bank = 0, Row = 0000, Col = 003, Data = 7c00
# At time 335265.000 ns WRITE: Bank = 0, Row = 0000, Col = 004, Data = 7c00
# At time 335270.000 ns WRITE: Bank = 0, Row = 0000, Col = 005, Data = 7c00

# At time 335275.000 ns WRITE: Bank = 0, Row = 0000, Col = 006, Data = 7c00

Can't you see now that it is working prefectly:

- A write every 5 ns (2x 100 MHz)

- We are in the same row

- The columns are incrementing linearly as expected

- No jumps

- No misses

- Everything working just smoothly.

Hopefuly all your confusion is gone now.

Regards,

JaaC

[nhungth]

Hi Sanjaac,

At the moment, I am the last-year student and I have to work with FPGA in my thesis. Can you help me how to use EDK 10.1 to control DDR-SDRAM? I am using Spartan 3E Starter Kit.

I am looking forward to hearing from you.

Best Regards,

Nhung.

[sanjaac]

Hi,

Well, the easy answer is: generate it on MIG (LogiCore), and build a controller for it according to the specs in the User Manual/Datasheet; there is where the fun is!

If you have more specific questions like those posted on the forum -did you read them already? did you try to dot it yourself already?-, maybe I could help. But I can not do your last year thesis.

Regards,

JaaC

[nhungth]

Hi Sanjaac,

Thank you for replying me!

Actually, I have already read some  related questions on this forum as well as other websites but everything seems too hard for a new person about FPGA like me. I also read the Datasheet but it is too long and I do not know where I can start. However, I will try to understand something in it and do the thesis myself.

One more thing, I never want to depend on another person in my work.

I am sorry if that is a silly question!

Best Regards,

Nhung.

[deepa]

Hi

I came across your post when I was looking for VGA controller code for Spartan 3E. I just want to know if we can create more than the available 8 colors in S3E? I see that we are using only 5 pins. Are more colors possible? Please let me know.

Thanks

[sanjaac]

Hi deepa,

Sure it is possible, with some HW rework. I have not done it, and -unfortunately- at this moment have no time to go look the schematics and figure out how to do it. Probably you are able to do it yourself, good luck and have fun!

JaaC