Spartan® Family FPGAs

[syalk1120]

Hi, I have a design of FPGA with DAC,and the interface is LVDS,  and I use OSERDES2 & OBUFDS to buffer output, the oscilloscope reads the swing is 600mV( clock rate is 122.88MHz),and  how could I bring this swing down?

also,I found it that when I changed the clock rate as 245.76MHz, the output swing was about 300mV, how to understand the difference result of that?

thanks.

[eteam00]

Hi, I have a design of FPGA with DAC,and the interface is LVDS,  and I use OSERDES2 & OBUFDS to buffer output, the oscilloscope reads the swing is 600mV( clock rate is 122.88MHz),and  how could I bring this swing down?

also,I found it that when I changed the clock rate as 245.76MHz, the output swing was about 300mV, how to understand the difference result of that?

What is the bandwidth of your oscilloscope?

What is the bandwidth of your oscilloscope probes?

Are the diff pair signals terminated?  If yes, where is the termination located, near the source or the load?

Where in the signal path are you probing with the scope?  Near the source?  Near the load?

-- Bob Elkind

[syalk1120]

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eteam00 wrote:

Hi, I have a design of FPGA with DAC,and the interface is LVDS,  and I use OSERDES2 & OBUFDS to buffer output, the oscilloscope reads the swing is 600mV( clock rate is 122.88MHz),and  how could I bring this swing down?

also,I found it that when I changed the clock rate as 245.76MHz, the output swing was about 300mV, how to understand the difference result of that?

What is the bandwidth of your oscilloscope?

What is the bandwidth of your oscilloscope probes?

Are the diff pair signals terminated?  If yes, where is the termination located, near the source or the load?

Where in the signal path are you probing with the scope?  Near the source?  Near the load?

-- Bob Elkind

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Hi,Thanks for your quick reply.

And the according test conditon are as following:

The bandwith of oscilloscope and probes are both 500MHz.

the diff pair  terminated at the receiver,i.e. DAC on chip 100ohm temination.

I tested the signal near the load.

[gszakacs]

I see a few possibilities:

• The DAC internal "100 Ohm" termination is higher than 100 Ohms.
• The characteristic impedance of the transmission line between the FPGA and DAC is lower than 100 Ohms differential.
• Power supplies of the FPGA are not within requirements for the I/O standard.  DS162 page 9, Table 8 shows the requirements for each standard.  Also there is a note that Vccaux must be 2.5V when using LVDS with -1L parts.

-- Gabor

[syalk1120]

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gszakacs wrote:

I see a few possibilities:

• The DAC internal "100 Ohm" termination is higher than 100 Ohms.
• The characteristic impedance of the transmission line between the FPGA and DAC is lower than 100 Ohms differential.
• Power supplies of the FPGA are not within requirements for the I/O standard.  DS162 page 9, Table 8 shows the requirements for each standard.  Also there is a note that Vccaux must be 2.5V when using LVDS with -1L parts.

-- Gabor

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Thanks,Gabor.

 After the further confirmation, I think the second possibility maybe the main cause.  and is there any way to test the impedance of  transmission line between FPGA and DAC on board?

[eteam00]

After the further confirmation, I think the second possibility maybe the main cause.  and is there any way to test the impedance of  transmission line between FPGA and DAC on board?

The textbook method is to rent a TDR (Time-Domain Reflectometer), or use a signal analyser.

The manufacturing approach would be to consult the board fab house on its stackup tolerances, add in the signal trace widths and spacing of the routed diff pair, and calculate the expected range of differential impedance.  This should have been done before the boards were ordered from the fab house.

The empirical method is to measure the amplitude and polarity of the reflections from the load end of the traces, and calculate the effective termination mismatch from the measured amplitude of the reflection.

Personally, I am not convinced.  Are you seeing failures in this interconnect, or are you simply concerned about the difference in waveform amplitude at different frequencies?  I suspect that your scope and probes are too 'slow' to provide consistent pulse amplitudes at the two frequencies you mention.

This is not what I would teach and encourage in a classroom, but there is little which can go wrong if the only problem is an incorrect parallel termination value at the load end of a single-load, single-source transmission line.  Yes, a reflection will result, but the load pin isn't affected much by the reflection unless there is a significant stub between the termination and the load pin.  Only the points between the load end and the source (including the source) will see the reflected wave.

Before you pillory me, consider series termination, where a signal edge hits an open circuit at the end of the transmission line.  The signal is reflected back toward the source, in phase, with 100% amplitude.  The load pin sees the in-phase reflection as a single, clean, double-amplitude edge when combined with the original unreflected signal.

The amplitude of the reflected wave will be proportional to the ratio of the transmission line impedance to the termination impedance.  As long as the reflected waveform is absorbed at the source end (and not re-reflected back to the load), you should have little worry.  If you must be wrong with your termination value, err on the high side.  This will tend to produce a bit of overshoot, while reducing the chances of a (fatal) dip or glitch in the middle of a clock edge.

For reference: the reflection coefficient is calculated by this equation:

 Zterm - Z0

------------- = ρ

 Zterm + Z0

Again, I suspect measurement gear as (at least) a contributing factor to the amplitude anomaly.

-- Bob Elkind

[gszakacs]

The empirical method is to measure the amplitude and polarity of the reflections from the load end of the traces, and calculate the effective termination mismatch from the measured amplitude of the reflection.

Another simple test would be to reduce the frequency much further.  If you see initially an overshoot

that settles down to the expected voltage, then you have an impedance mismatch.  If the amplitude

is just high and stays high, then either the FPGA is driving harder than advertised, or your 100 Ohms

is not 100 Ohms.

-- Gabor

[eteam00]

If you see initially an overshoot that settles down to the expected voltage,

Unless you are using active probes, the inductance of the scope probe and lead will provoke overshoot (or worse) in the scope display.  This also requires that you measure at the load, and at no other point in the trace(s).

The "DC" measurement which Gabor describes is a good approach.

-- Bob Elkind