Spartan® Family FPGAs

[calippso]

How can I tolerant input on 5V? :smileysad:

[rcingham]

If it's a custom board, add voltage translation buffers.

[calippso]

If possible, to use serial resistor?

[barriet · Accepted solution]

Not recommended.

More details here: http://www.xilinx.com/support/documentation/application_notes/xapp459.pdf (Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Generation FPGAs)

It should be noted the S6 IO design is similar to S3A's floating n-well.

bt

[barriet]

There's also a brief section in the S6 I/O user guide (ug381.pdf) called "Using Large-Swing Signals".

bt

[calippso]

Thanks for reply.

I have one question.

How about use to PCI Clamp diode?

[barriet]

The clamp diode should be enabled if and only if you used the PCI IO standard for the respective pin (PCI33_3 or PCI66_3). But I noticed they removed the "Voltage Clamps Using Internal Diodes Enabled by Using PCI I/O Standards" section from ug381.

You may want to open a webcase to find out why...

bt

[calippso]

yes~~ thanks a lot.

Have a good days.....:smileywink:

[drjohnsmith]

one other thing to remeber if forced to using 5v into and out of the fpga.

5v logic, the Vin L max is about 0.9 votls,

     ie it tends to be noisy,

          on the basis that a Vin H min is 2v2, that is still a big safe zone.

but if your clamping to say 3v3, then that 0.9 v needs to be addressed. 

If your driving out, then it could take some time for a 3v3 output to reach the levels required to 

    cross the threshold for CMOS 5V logic.

what I;m saying is you need to check,

   a random sample of one working in the lab would not be enough for me.

[eteam00]

How can I tolerant input on 5V [on Spartan-6] ?

Some methods which will work:

1.  Active level translation buffer (already mentioned in this thread).

2.  Internal PCI clamp diode, combined with external series resistor to limit clamp current.  Internal PCI clamp diode is not enabled until after FPGA is configured (for hot-swap capability), so 5V drive before configuration is complete will possibly (likely!) result in frying the FPGA input buffer.

3.  Extenal voltage divider.

4.  External voltage swing limiter.  Example:  5V I2C signal lines limited to 2.5V with FETs on SP605 board (see page 15 of SP605 schematics).

I believe the hot-swap issue is why the Voltage Clamps Using Internal Diodes Enabled By Using PCI I/O Standards section was removed from UG381, but this is pure speculation on my part.

-- Bob Elkind