Spartan® Family FPGAs

[neam]

hello everybody....

I am attempting to use the SP601 MIG reference design (RDF0005) by following the directions in XTP039,, but i have a problem:

ERROR:NgdBuild:604 - logical block 'gen_dbg_enable.my_ila_c3' with type 'ila'

   could not be resolved. A pin name misspelling can cause this, a missing edif

   or ngc file, case mismatch between the block name and the edif or ngc file

   name, or the misspelling of a type name. Symbol 'ila' is not supported in

   target 'spartan6'.

ERROR:NgdBuild:604 - logical block 'gen_dbg_enable.my_icon_c3' with type 'icon'

   could not be resolved. A pin name misspelling can cause this, a missing edif

   or ngc file, case mismatch between the block name and the edif or ngc file

   name, or the misspelling of a type name. Symbol 'icon' is not supported in

   target 'spartan6'.

ERROR:NgdBuild:604 - logical block 'gen_dbg_enable.my_vio_c3' with type 'vio'

   could not be resolved. A pin name misspelling can cause this, a missing edif

   or ngc file, case mismatch between the block name and the edif or ngc file

   name, or the misspelling of a type name. Symbol 'vio' is not supported in

   target 'spartan6'.

so what can i doing??

thanks in advance

[gszakacs · Accepted solution]

The items that are causing the error are ChipScope cores.  If you don't have a license

for ChipScope you should turn off the generation of these connections.  The name

of the components implies that they were generated based on a debugging enable

generic (or parameter).  You can probably find this in the top level instantiation of

the core.

-- Gabor

[neam]

I relly thank you for reply...

I removed now all Chipscope components(icon, ila and vio) , the synthesize is done but I fall in another problem :

ERROR:Pack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device.  Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as their packing might not have been completed.

although that I applied all the steps exactly as shown in the directions in XTP039...

so, what can i doing now??
did you have any MIG reference design except (RDF0005) To learn from it ...

 thanks in advance

[rcingham]

"The design is too large to fit the device."

You are going to need a bigger FPGA.
Or else drive the MIG-generated controllers 'ap' interface from logic inside the FPGA.

[gszakacs]

Too many bonded comps of type "IOB" found to fit this device.

This error can happen if you try to build the MIG core as the top level.  In that case all of the user

interface side signals (app_*) get mapped to I/O pins, and there aren't enough pins for that.

If you want to build a test project, you need to use the one provided as an example, or at least

build the MIG with the integrated synthesizable testbench.

- Gabor

[neam]

sorry , how can i cancel this solution option, i fall in many errors after the selection , and i need to Keep the door open for discussions..

[gszakacs]

Maybe a moderator can remove the solution from this thread, but it's probably

best to just start a new thread to ask any further questions.  If necessary you

can add a link to this thread by just copying and pasting the URL.

-- Gabor