Spartan® Family FPGAs

[evgenis1]

Hi,

ISE 12.x doesn't support partition-based partial reconfiguration (PR) flow for Spartan6.

I need it for a fairly simple PR in my project - single clock, 32-bit interface between static and reconfigurable region, a lot of unused logic and spare IOs. 

Difference-based approach won't work. 

I've been evaluating the following two approaches of a manual PR flow:

 - manually constraining proxy logic by building static+config_1 design, and porting constraints from .PCF to config_2

 - using FPGA pins to interface between static and reconfigurable regions (including clock and reset), so that there is no need for proxy logic.   

Any pros and cons, hidden problems?

Thanks,

Evgeni

[zumkehr]

Did you ever get help on this?

My main problem is finding information to do a manual flow.  I have seen papers saying they have done it but they are short on details.

For example, the automatic flow inserts "proxy logic"  for reconfigurable modules.  I have found no details of what these are except that they are LUTs.  You then have to know the switches for the tools to make sure the logic does not get swallowed or cause a DRC violation.

[evgenis1]

No, I didn't get any help on that. I agree that the isn't much documentation on how to do this manually.

We decided to go with a bigger S6 chip instead of messing around with PR. That 's unfortunate.

Thanks,

Evgeni