Spartan® Family FPGAs

[farazk86]

Hi,

K so im learning Verilog and kick start this process I bought the Basys2 Board containing the Spartan 3E board.

Im folloing Chu's Book; FPGA Prototyping (as it is based on the basys2 board)

So I learned how to code a simple counter... now what I want to do is to transfer this to the board and to display it on the board' s 7 segment display.

Below is the counter code matched with the code taken from the book to run the 7 segment display.

module  disp-hex-mux 
( 
input  wire  clk,  reset, 
input  wire  [3:0]  hex3,  hex2,  hexl,  hex0,  //  hex  digits 
input  wire  [3:01  dp-in,  //  4  decimal  points 
output  reg  C3:OI  an,  //  enable  I-out-of-4  asserted  low 
output  reg  [7:01  sseg  //  led  segments 
1; 
 //  constant  declaration 
//  refreshing  rate  around  800  Hz  (50  MH.z/2"16) 
localparam  N  =  18; 
//  internal  signal  declaration 
reg  [N-1:0]  q_reg; 
 wire  [N-1:0]  q_next; 
reg  [3:0] hex_in; 
reg  dp; 
//  N-bit  counter 
 //  register 
always  @(posedge clk,  posedge  reset) if  (reset) 
q_reg  <=  0; 
else 
q_reg  <=  q_next; 
//  next-state  logic 
assign  q_next  =  q_reg  +  1; 
//  2  MSBs  of  counter  to  control  4-to-1  multiplexing 
//  and  to  generate  active-low  enable  signal 
always  @* 
case  (q_reg[N-1:  N-2]) 
2'b00: 
begin 
an =  4'b1110; 
hex-in  =  hex0; 
dp =  dp_in[0]  ; 
end 
2'b01: 
begin 
an =  4'b1101; 
hex-in  =  hex1; 
dp =  dp_in  [1] ; 
end 
2'b10: 
begin 
an =  4'b1011; 
hex-in =  hex2; 
dp =  dp-in  [2] ; 
end 
default: 
begin 
an =  4'b0111; 
hex-in =  hex3; 
dp =  dp-in  [3] ; 
end 
endcase 
//  hex  to  seven-segment  led  display 
always  @* 
begin 
case (hex-in) 
4'h0  :  sseg  [6:0]  =  7  '  b0000001; 
4'h1:  sseg[6:0]  =  7'b1001111; 
4'h2:  sseg  [6:0]  =  7'b0010010; 
4'h3:  sseg  [6:0]  =  7'b0000110; 
4'h4:  sseg[6:0]  =  7'b1001100; 
4'h5:  sseg[6:0]  =  7'b0100100; 
4'h6:  sseg  [6:0]  =  7'b0100000; 
4'h7:  sseg[6:0]  =  7'b0001111; 
4'h8:  sseg  [6: 0]  =  7'b0000000  ; 
4'h9:  sseg  [6:0]  =  7'b0000100; 
4'ha:  sseg  [6:0]  =  7'b0001000; 
4'hb:  sseg  [6:0]  =  7'b1100000; 
4'hc:  sseg  [6:0]  =  7'b0110001; 
4'hd:  sseg  [6:0]  =  7'b1000010; 
4'he:  sseg  [6:0]  =  7'b0110000; 
default:  sseg  [6:0]  =  7'b0111000;  //4'hf 
endcase 
sseg  [7]  =  dp; 
end 
endmodule

 k so this is the code from the book where it wants to explain the 7 segment.

I would appreciate it if someone could explain the following.

 - Why are only the 2 MSB's used here and what is its importance in operating the 7 segment? and furthermore I do  not understand the case (q_reg[N-1: N-2]) related to it.. as in every case on what basis is the and and hex output declared?

 - Also I understand this code is taking inputs from another module.. so can I just transfer my counter output directly to the 7 segment using the last case.. " hex to seven-segment led display"

P.S. I have attached the block diagram from the book around which this code is based and hope it helps in some clarification.

thank you for your time and help

[eteam00]

To understand how the Basys2 is displaying 4 digits of 7-segment LED display, you need to understand

• how LEDs work
• how 7-segment displays work
• how time-multiplexing works

Here is a step-by-step tutorial for you.  You need to learn each step, through the section on time-multiplexing.

This will make the example project code much more clear.

-- Bob Elkind

[farazk86]

Hi,

Thank you for the link.. didnt know about that site..

now I did like suggested and am going through every step in detail..

Now I know this is the first step but I cant make sense of the below code.. and would appreciate a little commenting.

wire [3:0] PWM_input = cnt[23] ? cnt[22:19] : ~cnt[22:19];
reg [4:0] PWM;
always @(posedge clk) PWM <= PWM[3:0]+PWM_input;

 This is from making an LED glow.

i understand that in the first statement a wire PWM_input is declared and is set to a condition.. that if the MSB of cnt is high assign PWM_input to cnt[22:19].. otherwise to its not.... [Just dont understand the reasoning behind it]

then a 5 bit register is declared.. (which is not initialized.. so wont it have junk value?)

and why is it declred as 5 bit but in addition used only 4 bits.. and also why add it?

Im sorry if these are too new questions.. bbut im new and learning it.

Thank you for your time and responses.

[eteam00]

PWM = Pulse Width Modulation

PWM is used to switch the LED on and off.  Varying the ratio of ON to OFF time will vary the apparent brightness of the LED.  If the switching frequency is high enough, the human eye does not see the individual ON and OFF times, only a range of brightness which can vary from OFF through a range of DIM levels up to (fully) ON.

There is much written (and searchable) about PWM on the web.  On the same fpga4fun website there is a 'project' devoted to PWM.  There are several Xilinx app notes and example designs of PWMs.

i understand that in the first statement a wire PWM_input is declared and is set to a condition.. that if the MSB of cnt is high assign PWM_input to cnt[22:19].. otherwise to its not.... [Just dont understand the reasoning behind it]

PWM_input is a 4-bit value which is constantly counting up and down between 0 and 15.

then a 5 bit register is declared.. (which is not initialized.. so wont it have junk value?)

If it is not initialised, its beginning value is not important (an initial value is useful when simulating, though!)

and why is it declred as 5 bit but in addition used only 4 bits.. and also why add it?

All 5 bits of PWM are used.  The PWM[4] is the carry out (or overflow) from the 4-bit addition.

-- Bob Elkind

[farazk86]

Hi,

thanks for the reply.. I get it now :)

so I wanted to change my first project to make an LED glow..

so I wrote the code in xilinx and wanted to simulate it before I transfer it to my BASYS2 board.

but simulation is not working.. the output "led" is set to unknown(x)   = (

here is my code.. (the values are kept small for simulation purposes)

module led_glow(
    input clock,
	 output led
    );

reg [5:0]count;

always @ (posedge clock)
	begin
		count <= count+1;
	end
	
wire [3:0]PWM_in;

assign PWM_in = count[5]?count[4:1] : ~count[4:1];

reg [4:0]PWM;

always @ (posedge clock)
	begin
		PWM <= PWM[3:0] + PWM_in;
	end
	
wire out;

assign led = PWM[4];
//assign led = out;

endmodule

and here is the testbench I used... did many changes to it and then commented it out.. as I want to see the individual value change of each register to better help me understand.. if that makes any sense..

module led_glow_test;

	// Inputs
	reg clock;
	//reg [5:0]count;
	//reg [3:0]PWM_in;
	//reg [4:0]PWM;
	
	// Outputs
	wire led;
	localparam T = 100;
	// Instantiate the Unit Under Test (UUT)
	led_glow uut (
		.clock(clock), 
		.led(led)
	);
initial begin
	clock = 0;
	forever
		#T clock = ~clock;
end
	initial begin
		// Initialize Inputs
		//count = 6'b0;
		//PWM_in = 4'b0;
		//PWM = 5'b0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

why is this not working??

Thank you :)

[eteam00]

You have several registers in your design, and none of them are initialised.  You can set an initial value for these registers with a simple Verilog construct.  For example:

change

reg [5:0]count;

to

reg [5:0]count = 0;

This sets initial value of the count register to 0.  If count is not initialised, its value is unknown.  count + 1 is also unknown if count is unknown.

Happy simulating!

-- Bob Elkind

[farazk86]

ah.. I thought that too.. but if you see the commented section in the test bench.. i tried initializing all registers used.. but still it made no difference.. the led remained unknown..

also the output of the count register kept at 00000.. and did not change.. the only thing changing in the simulation is the clock =/

[farazk86 · Accepted solution]

update

K then so I finally managed to make it work..

it started working after I added a reset to the code.. the reset made it work.. the led output is now glowing as normal.

here is the updated and fixed code

module led_glow(
    input clock, reset,
	 output led
    );

reg [5:0]count;

always @ (posedge clock)
	begin
		if (reset)
			count <= 0;
		else
			count <= count+1;
	end
	
wire [3:0]PWM_in;

assign PWM_in = count[5]?count[4:1] : ~count[4:1];

reg [4:0]PWM;

always @ (posedge clock)
	begin
		if (reset)
			PWM <= 0;
		else
			PWM <= PWM[3:0] + PWM_in;
	end
	
//wire out;

assign led = PWM[4];
//assign led = out;

endmodule