Spartan® Family FPGAs

[don00700]

Communication receive setting values and stores in registers

and FPGA uses those values for internal working.

i think this will use fewer resources but it isn't.

here is a simple code of my think

=============================================

module TEST(

    input    clk,

    // receive data from communication module

    input    [7:0]    addr,

    input    [15:0]  data,

    // values for FPGA internal uses

    output  [15:0]  value0,

    output  [15:0]  value1,

    // ........

);

// register for store values

reg  [2047:0] MAIN_REG;

// store values in resiger

always @ (posedge clk)begin

    MAIN_REG[(addr*16)+:16] <= data;

end

// output values for FPGA use

assign value0 = MAIN_REG[(para_value0*16)+:16];

assign value1 = MAIN_REG[(para_value1*16)+:16];

// ......................

endmodule

==========================================

FPGA is xc3s700an

in actual code, in Device Utilization Summary,

Number of Slice Flip Flops : 33%

Number of 4 input LUTs : 142%(OVERMAPPED)

Number of occupied Slices : 156%(OVERMAPPED)

Total Number of 4 input LUTs : 148%(OVERMAPPED)

i think very inefficiencies in store & output values.

i'm looking for an efficient way... please help me

[rcingham]

My initial guess is that XST has interpreted your '*16' as multiplies rather than 'shift-by-4', which would require less logic. Don't know enough Verilog to tell you haw to change that.

What version of ISE tools are you using?

[gszakacs]

Your memory has two read ports - each one is a 16-wide 128:1 multiplexer.  That's what is eating up your

LUT resources.  This is exactly the sort of thing that a block RAM does well.  Why would you think that using

flip-flops would recude resource usage?

-- Gabor

[eteam00]

You are inferring a RAM incorrectly.  See the ISE Language templates in ISE Navigator (click on the lightbulb icon) for synthesis construct coding examples.

Have you defined "para_value0" and "para_value1"?

Are you writing to RAM on every clock cycle?

-- Bob Elkind

[don00700]

Thank you for the answer.

my project have ADCs and DACs

so i have to store each channels gain, offset and user changable values and so on..

problem is those values come from communication channel.

so FPGA have to store those values in FPGA registers,

because all values are used at the same time, i cannot use BRAM.

actually, I'm a student learning FPGA, my think is might be wrong.

i'm not sure you understand my intention, but i hope your advice.. :-)

[eteam00]

so i have to store each channels gain, offset and user changeable values and so on.. problem is those values come from communication channel. so FPGA have to store those values in FPGA registers, because all values are used at the same time, i cannot use BRAM.

If you look at your original code, only two registers can be accessed concurrently. This contradicts the reasoning that a BRAM cannot be used.

Perhaps you need to re-organise your design approach, with a better understanding of what connections (datapaths) are essential and which are not.

-- Bob Elkind