Spartan® Family FPGAs

[gederer]

Hi all,

is it possible to swap DDR3 data pins for improving layout?

e.g. route IO_L38N_M3DQ3_3 as net "DDR3_DQ4" to DQ4 on a DDR3 SDRAM Device

regards

Ed

[eteam00 · Accepted solution]

is it possible to swap DDR3 data pins for improving layout?

Let me rephrase your question to make it less ambiguous, because it's critically important to answer the question correctly and clearly:

Which DDR interface signals can be swapped between the FPGA device pins and the DRAM device pins on the board, in order to improve board layout?

Did I understand your question correctly?  If so, here is the answer --

Swapping DQ3 with DQ4 is completely OK.  Here are the swappable sets:

Set 1:  any of these pins can be swapped with one another, for either x8 or x16 DRAMs

{DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7}

Set 2:  any of these pins can be swapped with one another, for x16 DRAMs

{DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15}

Let's be absolutely 100% clear.  We are not discussing changing the FPGA pinout -- which MIGHT (pure conjecture on my part) adversely affect FPGA routing -- we are talking about swapping the connections of DQ bits in the circuit board schematics, from FPGA device pins to DRAM device pins.

There is one more opportunity for swapping, which applies ONLY for the use of a x16 DRAM.  You can swap upper and lower byte lanes, in their entirety.

These pins (lower byte lane):

{DQS, DQS_N, DM, DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7}

can be swapped 1 for 1 with these pins (upper byte lane):

{UDQS, UDQS_N, UDM, DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15}

None of the remaining DRAM pins may be swapped.  Ever.

- Bob Elkind

[gederer]

Hi Bob,

That's excactly what I needed to know, swapping only these pins :
{DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7}

Thank you for your fast reply.

warm regards
Ed

[thomas1974]

I assume swapping also address signals is (unlike as with SRAMs) not possble with DRAMs because of e.g. burst read operation.(?)

[eteam00]

SDRAM address pins are not swappable for a number of reasons:

• some bits are row only, some are multiplexed row and column
• A[10] is used for selecting precharge operations
• address bits are used as data bits for loading (writing) the MODE registers

In a DRAM datasheet, see the Commands Truth Table

-- Bob Elkind