Spartan® Family FPGAs

[kchalla]

Hi,

I want to generate clock with user configurable duty cycle. That means user will change the duty cycle in real time. i.e no new bitstream file. So i started with register definitions and configure with microcontroller.

I have started using PLL_BASE clock management component for Spartan-6. I have only one PLL_BASE component in use. I can generate clock with duty cycle with default value in generic map.

My problem is how can i make it configurable?

And the values are also real values, 20% duty cycle should be written as CLKOUT0_DUTY_CYCLE => 0.20

Do i need to make it in fixed point format? If yes what is the resolution?

   PLL_BASE_inst : PLL_BASE
   generic map (
      .........................................

      -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
      CLKOUT0_DUTY_CYCLE => 0.5,
      CLKOUT1_DUTY_CYCLE => 0.5,
      CLKOUT2_DUTY_CYCLE => 0.5,
      CLKOUT3_DUTY_CYCLE => 0.5,
      CLKOUT4_DUTY_CYCLE => 0.5,
      CLKOUT5_DUTY_CYCLE => 0.5,

      ...........................................

)

port map (

      ...........................................

);

Thanks in advance.

Best Regards,

Kiran

[bassman59 · Accepted solution]

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kchalla wrote:

Hi,

I want to generate clock with user configurable duty cycle. That means user will change the duty cycle in real time. i.e no new bitstream file. So i started with register definitions and configure with microcontroller.

I have started using PLL_BASE clock management component for Spartan-6. I have only one PLL_BASE component in use. I can generate clock with duty cycle with default value in generic map.

My problem is how can i make it configurable?

And the values are also real values, 20% duty cycle should be written as CLKOUT0_DUTY_CYCLE => 0.20

Do i need to make it in fixed point format? If yes what is the resolution?

   PLL_BASE_inst : PLL_BASE
   generic map (
      .........................................

      -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
      CLKOUT0_DUTY_CYCLE => 0.5,
      CLKOUT1_DUTY_CYCLE => 0.5,
      CLKOUT2_DUTY_CYCLE => 0.5,
      CLKOUT3_DUTY_CYCLE => 0.5,
      CLKOUT4_DUTY_CYCLE => 0.5,
      CLKOUT5_DUTY_CYCLE => 0.5,

      ...........................................

)

port map (

      ...........................................

);

Thanks in advance.

Best Regards,

Kiran

---

Generics are compile-time constants, so they can't be changed at run-time.

Depending on the desired clock frequency, a PWM is probably the right solution.

[kchalla]

Hallo bassman59,

thanks for your reply. As you said at the moment PWM is only the solution.

But for me its good to know that Generics cannot be changed during runtime.

Best Regards,

Kiran

[bassman59]

---

kchalla wrote:

But for me its good to know that Generics cannot be changed during runtime.

---

I suggest that you invest in a good VHDL text, because that fact is pretty fundamental.