Don't have a Xilinx account yet?

  • Choose to receive important news and product information
  • Gain access to special content
  • Personalize your web experience on Xilinx.com

Create Account

Username

Password

Forgot your password?
XClose Panel
Xilinx Home
Reply
Newbie
kuti
Posts: 2
Registered: ‎08-06-2013
0
Accepted Solution

Pack:2531 - The dual data rate register "clock_clk_5p3M" failed to join

I am trying to direct a generated clock with pll towards an out pin, using ODDR2 and  OBUF, however i got this error

"Pack:2531 - The dual data rate register "clock_clk_5p3M" failed to join    the "OLOGIC2" component as required"

 

Would you please help? see below the code.

 

ODDR2 #(
      .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
      .INIT(1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1
      .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
   ) clock_clk_5p3M (
      .Q(v_CIS_test_clk),     // 1-bit DDR output data
      .C0(s_CIS_test_clk),  // 1-bit clock input
      .C1(~s_CIS_test_clk), // 1-bit clock input
      .CE(1'b1),      // 1-bit clock enable input
      .D0(1'b1), // 1-bit data input (associated with C0)
      .D1(1'b0), // 1-bit data input (associated with C1)
      .R(reset),   // 1-bit reset input
      .S(1'b0)   // 1-bit set input
   );

  OBUF #(
      .DRIVE(12),   // Specify the output drive strength
      .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
      .SLEW("SLOW") // Specify the output slew rate
   ) OBUF_CIS_test_clk (
      .O(CIS_test_clk),     // Buffer output (connect directly to top-level port)
      .I(v_CIS_test_clk)      // Buffer input
   );

Moderator
vemulad
Posts: 2,391
Registered: ‎09-20-2012
0

Re: Pack:2531 - The dual data rate register "clock_clk_5p3M" failed to join

Hi,

 

The outputs of ODDR2 should go to the output PAD's through the OBUF, and the outputs of ODDR2 cannot be looped back into the FPGA's internal logic. This is shown below. 

 

new1.png

 

Please check in case if you are looping back from ODDR2 ouputs which is causing the problem. Also post the complete error message.

 

Thanks,

Deepika.

--------------------------------------------------------------------------------------------
Google your question before posting.
If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Newbie
kuti
Posts: 2
Registered: ‎08-06-2013
0

Re: Pack:2531 - The dual data rate register "clock_clk_5p3M" failed to join

Hi Deepika,

 

Thanks a lot, problem solved, the output of my ODDR2 was looped back into the FPGA's internal logic.

 

Regards

 

Kuti

Moderator
vemulad
Posts: 2,391
Registered: ‎09-20-2012
0

Re: Pack:2531 - The dual data rate register "clock_clk_5p3M" failed to join

Hi Kuti,

 

Good to learn that it works.

 

Please mark the thread as solved by accepting the post as solution.

 

Thanks,

Deepika.

--------------------------------------------------------------------------------------------
Google your question before posting.
If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Moderator
smarell
Posts: 1,058
Registered: ‎07-23-2012
0

Re: Pack:2531 - The dual data rate register "clock_clk_5p3M" failed to join

Marked as an answer for future references.
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.