Spartan® Family FPGAs

[jasonzou]

Device 500E

ISE version 12.4

Target:I need 2 clock. 1st clock used in inside of FPGE.2nd clock used as external clock in pcb. 

 I used the the output of dcm clock and its inverse clock to driver ODDR2.

Problem: I can used Scope to view the ODDR2 input C0,C1.They are 128Mhz.The max voltage value is 2.5.DDR_CLKFX_OUT max voltage valuse is 100mv. And Its frequents was wrong.

Here is my code.

	ODDR2 	#(
				.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
				.INIT(1'b0), // Sets initial state of the Q output to 1?b0 or 1?b1
				.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
				) ODDR2_inst_FX (
							.Q(DDR_CLKFX_OUT), // 1-bit DDR output data
							.C0(U1_C0_IN_FX), // 1-bit clock input
							.C1(U1_CLKFX_INV_IN), // 1-bit clock input
							.CE(1'b1), // 1-bit clock enable input
							.D0(1'b1), // 1-bit data input (associated with C0)
							.D1(1'b0), // 1-bit data input (associated with C1)
							.R(1'b0), // 1-bit reset input
							.S(1'b0) // 1-bit set input
							 );
 BUFG  U1_CLKFX_BUFG_INST (.I(U1_CLKFX_BUF), 
                            .O(U1_C0_IN_FX));
 INV   U1_INV_INST_FX     (.I(U1_C0_IN_FX), 
                             .O(U1_CLKFX_INV_IN));

[eteam00]

Problem: I can used Scope to view the ODDR2 input C0,C1.They are 128Mhz.

The max voltage value is 2.5.DDR_CLKFX_OUT max voltage valuse is 100mv. And Its frequents was wrong.

Your problem description is unclear.

If you are generating a 128MHz clock from a S3E DCM, and you are using this 128MHz clock both internally and externally, the nominal implementation is (should be) quite simple.  For example (using Verilog):

ODDR2     #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst_FX (
    .Q(DDR_CLKFX_OUT), // 1-bit DDR output data
    .C0(U1_C0_IN_FX),  // 1-bit clock input
    .C1(~U1_C0_IN_FX), // 1-bit clock input, uses "internal" clock inverter
    .CE(1'b1), // 1-bit clock enable input
    .D0(1'b1), // 1-bit data input (associated with C0)
    .D1(1'b0), // 1-bit data input (associated with C1)
    .R(1'b0),  // 1-bit reset input
    .S(1'b0)   // 1-bit set input
     );
BUFG  U1_CLKFX_BUFG_INST (.I(U1_CLKFX_BUF), .O(U1_C0_IN_FX)); // clock buffer for DCM output

There is no need for two DCM outputs, one will suffice.  The buffered copy of the DCM output (U1_C0_IN_FX) is used internally as the global fabric clock, as well as the ODDR2 clock.

In S3E devices, a BUFG clock output can drive both .C0 and .C1 ODDR2 pins in either polarity.  Polarity inversion is implemented 'magically' (perhaps in the ODDR2 block, perhaps in the interconnect switch matrix, it matters little for your purposes).  Using Verilog, the simple logic inversion ("~") in the .C1 port connection is sufficient.

NOTE:  Code for clock forwarding is a bit less simple for VHDL than for Verilog.  The logic inversion (using "~") at the .C1 port assignment is not supported in VHDL.

NOTE:  "internal" clock inversion, in some device families, may not be available for all clock sources.  For example, Spartan-6 BUFIO2 clocks cannot use the "internal" clock inversion (both clock polarities must be generated using two BUFIO2 buffers).

Additionally, a single-ended output port declaration for output signal DDR_CLKFX_OUT needs to be instantiated in the source code top level, with an IOSTANDARD declaration in your .UCF file (example below)

NET "DDR_CLKFX_OUT" IOSTANDARD = "LVCMOS25";

Does this make sense?

-- Bob Elkind

[jasonzou]

Thanks.Today i define a lower  DCM output clock frequence.(64Mhz).

I can view the ODDR2 ouput in my scope.

In my opinion,Output voltage has its default vaulue.If i did not define IO standar ,it would use default value.

The IO could not meet 128Mhz Square wave need ?

[eteam00]

The IO could not meet 128Mhz Square wave need ?

Your meaning is uncertain.

• The package pin and output buffer can support 128MHz output.

• You should define the output signaling IOSTANDARD being used, the "default" is too vague and may not match your VCCO.

• If you are using an oscilloscope, verify that your 'scope and probes are suitable for measuring 500MHz or higher frequencies.  A 150MHz scope is not adequate for measuring 128MHz square waves.

-- Bob Elkind