Spartan® Family FPGAs

[fenix_k]

Hello

I ask for help with SD card low level controller. It's code from which I learned: sd code . It's SPI bus mode and finally  I can transfer data from card to FPGA. But speed is too low for me. I need more than 20 MBit/s. I could use HighSpeed mode (SD bus). Now it's not problem for me to initialize like here (i dont use all commands, only these for HS mode):

After command CMD6 I need to work with 50MHz which is the frequency in 'clk' signal (in initialization I use limited clock obviously), but as you can see in code 'sclk' clock provided to card can be at most half of 50MHz (if I understand that FSM good -> sclk_sig <= not sclk_sig;). Could you suggest me some idea how to communicate with card after CMD6? What could be the best way to provide 50MHz in that project?

Regards,

FK

[eteam00]

I ask for help with SD card low level controller. It's code from which I learned: sd code .

Have you asked the designer who originally wrote and debugged the code for help?

It's SPI bus mode...

In the SD card specifications, this is called SPI bus mode, but the data transfer protocol is considerably different than a typical SPI flash memory.

... and finally I can transfer data from card to FPGA. But speed is too low for me. I need more than 20 MBit/s.

Generally speaking, using the SPI bus mode for SD card data transfers is a dicy proposition.  Different SD cards (and controllers) may implement this mode differently, and data transfer performance is likely not a high priority for the folks who designed the SD cards.

I could use HighSpeed mode (SD bus).

This requires licensing the SD card specification, as this transfer protocol is not in the public domain.  This is the SD card consortiums means for maintaining compatibility standards.  Discussing the specifics of a proprietary or confidential specification would probably not be allowed in these forums

but as you can see in code 'sclk' clock provided to card can be at most half of 50MHz

As of level 2 of the SD card specification, the interface clock can be up to 50MHz (not 25MHz).  This is public, disclosed information.  Having said that, not all SD cards must (or will) support 50MHz bit clocks in SPI bus mode.  Furthermore, if you study the SPI bus mode as publicly described and discussed, you will quickly realise that a faster or slower bit clock may have no effect whatsoever on data access time.  Access time for SD cards is defined by nS or uS, depending on the design of the SD card, and not by number of bit clock cycles.

If you have minimum performance requirements for your design, SD cards in general are a dicy proposition and using SPI bus protocol compounds your problems.  You will be hard-pressed to find inexpensive SD cards with guaranteed minimum performance characteristics, especially for SPI Bus mode.  The card you purchase and test today may not match the card (same manufacturer and model) which you purchase next month.

-- Bob Elkind

[fenix_k]

Thanks for your reply.

I didn't asked the designer for help, I hope it is easier to get help here.

Assuming that my card can work in High Speed SD Bus Mode and I would like to use it and omit conversation about SPI Bus Mode, because I'm sure it is not enough. Could you help me then with FPGA side ? It's totally not commercial usage. Just I'd like to know how to proceed in order to provide maximum clock (50MHz which comes from external source and all the circuit works with it) to my card (which need in High Speed Mode 50 MHz). Maybe I should try to increase my frequency twice?

[eteam00]

If you are asking how to output a 50MHz clock, using a 50MHz internal FPGA clock, the answer is simple:  clock forwarding.

This is one of the FAQ topics in the New Users Forum README thread, post #2:

clock forwarding to an output pin link#1  link#2

-- Bob Elkind

[fenix_k]

That was useful information, but not what I need.

My problem is that circuit made in this convention like in link above is reacts to signal:

if (sclk_sig = '1') then 
     if (bit_counter = 0) then
...

and it happens in many states.

'sclk_sig' is switched every 'clk' tick so it has half frequency of 'clk'. Now if I have 50MHz clock, I can work with card in Default Speed Mode which needs 25MHz ('sclk' provided to card has this frequency). But I don't know how to use possibility to work in High Speed Mode which needs 50MHz. It's all my 'clk' frequency so I have to stop using 'sclk' signal switched like this: sclk_sig <= not sclk_sig; and have to use clock directly provided to card.

And my trouble is with this: if (sclk_sig = '1') then.

My first solution: I thought that if I remove all of that condition statements and all process reacts to rising_edge(clk), it will be working. But it doesn't.

Second is that I could create 100MHz clock in DCM, but ISE shows that I can run this circuit with max frequency about 90MHz....

I don't have much experience in FPGA and VHDL so I'm asking for help how to deal with it.

[eteam00]

If you are waiting for concise and specific answers to your questions, you will need to be patient.  You need someone:

• who has an understanding of SPI mode SD card interface
• who has time to understand your design needs
• who has time to reverse engineer 280 lines of someone else's code
• who has time to explain to you how how the copied code works and what changes (if any) need to be made

It may be a while until a volounteer with the right qualifications has the time and inclination to accept this task.  Even then, you will still need to understand the interface protocol and the copied code for yourself.

Perhaps this is a bigger project than you are ready to take on.  You might consider learning VHDL and FPGA design with some simpler design problems.  Work your way up to more complicated projects as you gain some experience and confidence.

When you are ready to take on the SD card interface, perhaps you might consider simulating the operation of the code you are using.   Simulation is an essential aid to help you understand the code you are trying to use, especially the code you did not personally write.

When you use extensive amounts of code written by someone else, there are always two problems which must be overcome:

• Customising the code to your specific needs and design.
• Learning (understanding) the new code well enough to debug your design in the case that it does not work as intended from the outset.

-- Bob Elkind

[fenix_k]

So I still have problem. I think that is because of bad clock condition. Now I'm in situation that I need to send command to a card and the card should send me response. If I do that with 25MHz clock with duty cycle about 44/56, the card sends response. If clock is 50MHz and duty cycle about 35/65, I don't see response on wire.

I tried to use Clock Forwarding techinque as you suggested, but don't see significant improvement in duty cycle (maybe 1-2% better). Here is how I used OFDDRRSE register:

inv_clk3 <= NOT clk3;

OFDDRRSE_inst : OFDDRRSE
   port map (
      Q => output_clock, -- 1-bit output data
      C0 => clk3, -- 1-bit clock input
      C1 => inv_clk3, -- 1-bit clock input
      CE => '1',  -- 1-bit clock enable input
      D0 => '0',   -- 1-bit data input (associated with C0)
      D1 => '1',   -- 1-bit data input (associated with C1)
      R => '0',    -- 1-bit reset input
      S => '0'     -- 1-bit set input
   );

sclk <= output_clock;

  Clk3 is from CLK0_OUT DCM's output. sclk is provided to the card.

Could you help with correct forwarding?

[rcingham]

> Could you help with correct forwarding?

Try studying this post & thread...
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/how-to-instantiate-ODDR-block/m-p/232589/message-ui...

[eteam00]

Could you help with correct forwarding?

Already answered in post #4 in this thread.

-- Bob Elkind

[fenix_k]

Obviously I read it previously. I tried to do it like in threads you both pointed, in attachment is simple code. In ucf file I have just LOC for 'clk_in' input and 'sclk' output. Here is how 'sclk' looks:

I would like to know if I'm doing something wrong or it is impossible to have better output clock.