Spartan® Family FPGAs

[kurgan]

Hello!

I develop board based on Spartan-6 and now impossible to know how Spartan-6 will used.

I need to develop power supply for maximum power consumption.

Could you point me to document about SPARTAN-6 LXT Power Data (maximum current value)

for VCCint, VCCIO, VCCpll, etc., please?

-- Regards, Victor

[eteam00]

If you already have a Spartan 6 design "coded up" in ISE, your best bet for power estimation is the power analyser applet within ISE Navigator (under the TOOLS menu, I believe).

If you don't already have your FPGA design near complete, then go to the Spartan 6 docs page, and download the Power Management User Guide.  It has a power estimation section.  And while you are at the Spartan 6 docs page, you might want to collect the other docs you should read before you finish your board (or FPGA) design.

As for designing for "maximum power", don't overlook the fact that an FPGA consuming "maximum power" will require exotic ($$) cooling.  As a practical consideration, you don't need to provide any more steady-state power than your FPGA and FPGA package can realistically dissipate without exceeding thermal operating range.  That gives you a rough ceiling on steady state power you need to provide (give or take current consumed off-chip, such as IO current).

-- Bob Elkind

[kurgan]

Hello.

Thank you for answer.

I haven`t yet FPGA desing. My schematic and board design similar to development board.

And I haven`t any data about end-user application or FPGA resource usage.

But how dev. board vendors develop power for FPGA boards?

-- Victor

[eteam00]

But how dev. board vendors develop power for FPGA boards?

One or more of the following:

1.  Build prototype and test it, with actual FPGA design

2.  Experience

3.  Over-design the power supplies (doesn't cost much for component upgrades to over-design)

- Bob Elkind

[hirschdaumen]

TI has some rough estimates that you can use: Spartan 6 Series Power Management. For accurate numbers, use the power estimator.

[kipingram]

This is a frustrating answer.  I'm interested in the same question:  MAXIMUM power handling capability.  I have not implemented my design yet - I want to send out my boards for fab and assembly *before* thinking about what's inside the FPGA.  That's supposed to be one of the advantages of using FPGAs, after all.

Most of the literature I've found has to do with hibernation, suspend, etc. etc. etc.  Applications that are trying to be low power inherently.  I am targeting a massively packed logic application that will be running 24/7.  My whole goal is to achieve the largest amount of compute activity that I can achieve in the unit - I need to now how many watts of power I need to be able to suck out of the thing with my cooling system when it is running *balls to the wall*. 

That *should* be a well-defined number - someone should have investigated that.  "Run the power estimator" is a lame and useless answer.  "Prototype it and see what happens" is equally lame and useless.

I just need to know the maximum amount of heat the logic can generate, or the maximum amount of power the internal power routing can support.  I can then design a suitable heat extraction system, or else I will find that my ability to extract heat is the limit, which is a just fine answer - I just need to know how much power and cooling to design for.

Regards,

Kip

[mcgett]

>I have not implemented my design yet - I want to send out my boards for fab and assembly *before* thinking

> about what's inside the FPGA.

You have actually thought about what needs to be inside the FPGA if you have created a board schematic.  You will have decided what types of interfaces will be used, how fast the will operate, selected clock component frequencies and have at least a somewhat specific reason for developing the board that you used to select the specific device that will be used on the board.

If you have not already completed at least a bare bones implmentation of the IO interfaces you should do so quickly to confirm that you have made the right pinout choices for IO and clocks.

> That *should* be a well-defined number - someone should have investigated that.  "Run the power estimator" is a

> lame and useless answer

FPGA power is not a well-defined number as it completely dependent on the design that is implemented in the FPGA. Running the power estimator is the only reasonable way to determine the expected power consumption for the design. If you don't want to think about it then enter 100% of the logic resources with a 100% toggle rate running at the clock frequency that you are using.   This will produce a number that is extremely high, but it is one that will not be exceeded.