Spartan® Family FPGAs

[airturk]

Dear Members;

 I have an SP605 design that has a system synchronous interface with its corresponding Offset In constraint (which is currently fails.) I am using Xilinx 12.4. 

The data signals are RxD[?] and clock is the RxClk. Here are their constraints in my ucf file:

NET "RxD[?]" TNM = "RxData";
TIMEGRP "RxData" OFFSET = IN 0.5 ns VALID 1.5 ns BEFORE "RxClk" RISING;
TIMEGRP "RxData" OFFSET = IN 0.5 ns VALID 1.5 ns BEFORE "RxClk" FALLING;

which fails, here are the results from the static timing report (I am only showing the "RISING" as an example):

Timing constraint: TIMEGRP "RxData" OFFSET = IN 0.5 ns VALID 1.5 ns BEFORE COMP "RxClk"         "RISING"; 
  4 paths analyzed, 4 endpoints analyzed, 2 failing endpoints 
  2 timing errors detected. (2 setup errors, 0 hold errors) 
  Minimum allowable offset is   0.576ns. 
 -------------------------------------------------------------------------------- 
  
 Paths for end point Inst_rgmii_gmii_rx/RXD04_DDR_REG_INST (ILOGIC_X17Y55.D), 1 path 
 -------------------------------------------------------------------------------- 
 Slack (setup path):     -0.076ns (requirement - (data path - clock path - clock arrival + uncertainty)) 
   Source:               RxD<0> (PAD) 
   Destination:          Inst_rgmii_gmii_rx/RXD04_DDR_REG_INST (FF) 
   Destination Clock:    GmiiRxClk rising at 0.156ns 
   Requirement:          0.500ns 
   Data Path Delay:      2.409ns (Levels of Logic = 2) 
   Clock Path Delay:     1.852ns (Levels of Logic = 4) 
   Clock Uncertainty:    0.175ns 
  
   Clock Uncertainty:          0.175ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
     Total System Jitter (TSJ):  0.050ns 
     Total Input Jitter (TIJ):   0.000ns 
     Discrete Jitter (DJ):       0.200ns 
     Phase Error (PE):           0.050ns 
  
   Maximum Data Path at Slow Process Corner: EnetRxD<0> to Inst_rgmii_gmii_rx/RXD04_DDR_REG_INST 
     Location             Delay type         Delay(ns)  Physical Resource 
                                                        Logical Resource(s) 
     -------------------------------------------------  ------------------- 
     P19.I                Tiopi                 1.310   RxD<0> 
                                                        RxD<0> 
                                                        RxD_0_IBUF 
                                                        ProtoComp2897.IMUX.23 
     ILOGIC_X17Y55.D      net (fanout=1)        0.184   RxD_0_IBUF 
     ILOGIC_X17Y55.CLK0   Tidock                0.915   Inst_rgmii_gmii_rx/RxDdrData<4> 
                                                        ProtoComp2973.D2OFFBYP_SRC.1 
                                                        Inst_rgmii_gmii_rx/RXD04_DDR_REG_INST 
     -------------------------------------------------  --------------------------- 
     Total                                      2.409ns (2.225ns logic, 0.184ns route) 
                                                        (92.4% logic, 7.6% route) 
  
   Minimum Clock Path at Slow Process Corner: EnetRxClk to Inst_rgmii_gmii_rx/RXD04_DDR_REG_INST 
     Location             Delay type         Delay(ns)  Physical Resource 
                                                        Logical Resource(s) 
     -------------------------------------------------  ------------------- 
     J22.I                Tiopi                 1.126   RxClk 
                                                        RxClk 
                                                        Inst_rgmii_gmii_rx/PHY_RXCLK_IBUFG_INST 
                                                        ProtoComp2897.IMUX.13 
     BUFIO2_X3Y11.I       net (fanout=1)        1.644   Inst_rgmii_gmii_rx/PhyRxClkBuf 
     BUFIO2_X3Y11.DIVCLK  Tbufcko_DIVCLK        0.105   SP6_BUFIO_INSERT_ML_BUFIO2_5 
                                                        SP6_BUFIO_INSERT_ML_BUFIO2_5 
     DCM_X0Y5.CLKIN       net (fanout=1)        0.641   Inst_rgmii_gmii_rx/RXCLK_DDRCLK_GEN_INST_ML_NEW_DIVCLK 
     DCM_X0Y5.CLK0        Tdmcko_CLK           -3.786   Inst_rgmii_gmii_rx/RXCLK_DDRCLK_GEN_INST 
                                                        Inst_rgmii_gmii_rx/RXCLK_DDRCLK_GEN_INST 
     BUFGMUX_X2Y4.I0      net (fanout=1)        0.635   Inst_rgmii_gmii_rx/RxDcmClk0 
     BUFGMUX_X2Y4.O       Tgi0o                 0.197   Inst_rgmii_gmii_rx/PHY_GMIICLK_BUFG_INST 
                                                        Inst_rgmii_gmii_rx/PHY_GMIICLK_BUFG_INST 
     ILOGIC_X17Y55.CLK0   net (fanout=41)       1.290   GmiiRxClk 
     -------------------------------------------------  --------------------------- 
     Total                                      1.852ns (-2.358ns logic, 4.210ns route) 
  

Here the input clk goes through IBUFG, DCM and BUFG. 

I am thinking of adding delay to meet the timing using IODELAY? However I was wondering if this is the best method to solve this particular setup timing problem?

Recommendations are appreciated. 

Regards, 

[airturk]

I am also currently trying the following:

My design includes a dcm, and adjusting the clock phase in order to balance the setup and hold margins at the internal register.

The OFFSET IN table in the Data Sheet section of the timing report lists the recommended clock phase adjustment to equalize the setup and hold margin.

[eteam00]

Your timing constraints are much too tight, and are also incorrect, for the Marvell 88E1111 RGMII interface, based on the 88E1111 datasheet, whether or not you use the RX_CLOCK delay mode.

If you disagree, please elaborate.  Keep in mind that the 10-year-old 88E1111 datasheet is (still) covered by NDA, and is not public information.

-- Bob Elkind

[airturk · Accepted solution]

Thanks Bob, you are right! 

However I made a mistake stating that I am targetting an SP605 board. I was actually targetting a custom board which should be able to meet this constraint. 

I got rid of the "offset in error" by adjusting the phase shift from the dcm to correct the incoming clock. 

Thanks !!!