I'm a bit confused on the Spartan 6 clocking when moving from the io clocking region to the fabric. Say your have a 200Mhz external clock that is synchronus with a data stream being used to clock an iserdes2... and your wanting to derive a gated clock in the fabric for block memory writing or data comparison etc. Core gen uses a bufg to buffer the clk_div from a BUFIO2_2CLK. Is there an acceptable method to use that bufg in the fabric for non clock input logic other than use a higher frequency clock manager resource and syncing the two frequency domains? Can you use combinatorial logic with the serdes strobe to derive timing?
not sure what you mean here, you can use the divided CLOCK from a BUFIO2 via a BUFG to clock the fabric or you can use a PLL to generate a different clock.
