Sorry, 1st post did not accept the attachment.
Circuit where input signals get held at a low level after Xilinx is configured. As a test, I produced a simple design consisting of: input pad-> buffer -> output pad. Input signals are present before configuration but are held low after configuration. This happens whether the Xilinx is progammed via JTAG or via XCF01S configuration PROM. I/O standards defined have been default, LVTTL, and LVCMOS33. Vcco for the bank is 3.3V. Input signal on GCLK7 (bank0) is not affected but input signals on all other bank 0 and bank 1 pins are affected including signal of GCLK6 (bank 0), GCLK5 (bank 1) and GCLK4 (bank 1). PCB schematic attached.
Any and all help is appreciated.
