Spartan® Family FPGAs

[alexgiul]

Hi Sanjaac,

thanks for your reply...with attribute "soft" now the design compile!!!!

I test the first task "the ddr initialization" and everything goes well.

Now I would write some data, but I do't understand well the timing diagram on UG086 page 254 figure 7-9 (see the attach)

my first question : what is D0,D1, Dx..? is D0 a word of 4 byte?So every burst I'll write 32 bytes of data?

[sanjaac]

Hello Alex.

Since it is a dual data rate memory, 16 bits wide, each tick of clk90 (which is the same as clk0, and in my case is a 100 MHz clock) writes 2x 16 bit words. This diagram is for a burst length of 4, which is also what I use in my design. So, each of those bursts writes actually 8x 16bit words. In my case I go a bit further, in the sense that I execute the burst_done cycle only when a full row is written, thus boosting the access time.

The generation and control of those signals is what goes inside the huge State Machine, which as I said, also generates the Dx data and Rows where to write to / read from. Soon I will post a cleaner code, which isolates this and can be used more effectively.

Regards.

[sanjaac]

Correction:

"[...] clk90 (which is the same as clk0, [...]" clk90 has the same rate as clk0, but is phase shifted 90 degrees.

[sanjaac]

Hi,

The new stuff is posted to the theread "Image from DDR to VGA - Spartan3E kit "

Regards.

[deepika.ahlawat03@gmail.com]

Hi Jaac

can you please share what code did you use to implement the memory(ddr). You have written that you implemented TestMemory App..so can you please share its source code as I am unable to open your project in Xisilinx ISE 12.3..It says that the older format project has some files missing. So just share the TestMemory app code and rest I will implement on my own.

Thankx in advance

[sanjaac]

Hi,

It was a customer project, I can not share the sources more than what I already did on the forum.

Good luck,

JaaC