Spartan® Family FPGAs

[jtex]

Hello,

I am designing with a Spartan 6 (currently using SP605 board but will eventually design our own).  I am using ISE 13.4 tools.  I am using an I/O pin as an output to control the "power on" timing of another part on the board.  This pin MUST stay low during and after configuration of the Spartan 6 at power up (the default value in the design is 0).  The pin should only go high when the design intentionally sets it high.  Even a small glitch on the pin before this time could destroy an expensive part.  The pin also needs to go low and stay low at power down.

What is the best way to design this?

I think I read that an external pull down resistor of 1K or less could work.  Is this correct?  Is there a better way?

Thanks in advance for any help.

Ron

[austin]

Ron,

All user IO pins are designed to be tristate (high impedance) until the configruation is loaded, and the part starts up.

That said, what happens as the power itself is being applied?  With 0v on Vcco, the IO pin "looks" like a diode to ground, so if you have a 1K ohm resistor to ground, it will still look like 0v at that point, as long as your source current (to make the measurement) is weak (from an impedance at least 10 times gretaer than the pull down).

Understand, that an IO pin also "looks" like 5 picofarads to Vcco, and 5 picofarads to ground, so if the Vcco turns ON very very fast, the IO pin will rise to 1/2 Vcco (for a very very short time, if there is a 1K resistor to ground).  That time, if the Vcco rose instantly (impossible) is ~ 0.7 * 1K ohms * 10 picofarads, or ~ 7 picoseconds.

Since you can not turn the power on that fast, the pin will look like 0 volts (with its 1K ohm resistor to ground), until your design takes over (which is what you want).

It is also important to note that the sequence of power ON, Vccint, Vccaux, then Vcco, is what we test on every part, so you should either power ON in the same sequence, or "all at once."

As the three supplies are roughly inncrasing in voltage (Vccint = 1v, Vccaux=2.5v, Vcco=2.5 or 3.3v) a similar sized (amperage) power supply system, with a similar capacitance (for power filtering and bypassing that is roughly equal on all) will mean that the sequence will always happen, as described.

Bottom line?  Yes, a 1K resistor to ground should work just fine.

[jtex]

Austin,

Thanks for the answer.  It looks like this will work for us.

Just for the sake of my own understanding, however, could you explain what you meant by:

"as long as your source current (to make the measurement) is weak (from an impedance at least 10 times gretaer than the pull down)"

I don't think that I totally understood that part.

Thanks again for your reply

Ron

[austin]

Ron,

Typically, to sense the voltage at a pin with no driver, one uses a pullup resistor.  The microprocessor you are using may have one (check).  if it does, and it is 1K, then the 1K pull-down is insufficient.

[rcingham]

> Even a small glitch on the pin before this time could destroy an expensive part.

How expensive?
Expensive enough to justify the cost of another (quite cheap) part between the FPGA and it?

[jtex]

Yes,  $500 - $1000.

[rcingham]

You might wish to consider using a supervisor chip, such as a MAX16057 (other suppliers of similar parts are available). The RESET# is guaranteed to stay low during power-up, and it has a 'Manual Reset' input that the FPGA can eventually drive to '1' to release the microprocessor. Cost: a couple of bucks...

[juergenatduerr]

If your "Power On" goes to a voltage controller chip, I assume it switching at around 50% VCC.

You might place a RC-filter in series in between the nodes (FPGA-output-Pin and pulldown-R) and the input Pin of the Chip. This is slow, but mostly fine for power regulator control.

This prevents any glitches or anything else from affecting the Pin, no matter, what happens with the FPGA or what kind of EMI occurs. The capacitor will keep the input pin low until it is "strongly" driven by the FPGA for a certain time.

In security apps, you can even place 2 Cs in parallel, because one of them might get unsoldered or get damaged in way, that the capacity is lost. The same can be done with the pulldown-Rs. Perhaps 2k in parallel might do.

For the opposite meaning, the maintainance of the function, the load R's  and the FPGA Pins might be doubled too.

The function then can only be ruined, if one of the caps, gets short cutted. But only the function is lost, the expensive device stays fine.