Spartan® Family FPGAs

[diegoroman17]

Hi,

Please I need help with a PCI card design. I am using a Spartan-6 LX Family for design a PCI card compatible with PCI Specifications 3.0. The documentation of Xilinx say that is necessary use a regulator voltage of 5V to 3.3V +-5% for VCCO bank that I use for connect signals of PCI bus. I understand this consideration and I use this regulator for PCI bank and other bank for I/O pins of general purpose. Now I don't understand How route PCI signals? With respect to which power plane should route the signalsof pci bus? The PCI Specification 3.0 say that should be route the signal with respect to 3.3V power plane but now I have two power plane of 3.3V, the 3.3V of PCI bus power plane and the 3.3V of regulator for VCCO power plane. Thanks for your help

Diego Cabrera

[eteam00]

Diego,

Are you designing a PCI card for sale, or for internal (proprietary) use?  This makes a difference, because some aspects of the PCI specification can be overlooked if your usage is constrained to "private" use.  If designing PCI devices for resale, where you have no control over usage or application, then strict adherence to the PCI specification is very important.

Now I don't understand How route PCI signals?

You should study this, or solicit the advice of an experienced board designer to help you and review your board layout design.

With respect to which power plane should route the signalsof pci bus? The PCI Specification 3.0 say that should be route the signal with respect to 3.3V power plane

Do you have a specific requirement for a separate 3.3V PCI supply?  I know of no general reason why the 3.3V supply for PCI devices must be isolated from a 3.3V supply used by other 3.3V devices.

but now I have two power plane of 3.3V, the 3.3V of PCI bus power plane and the 3.3V of regulator for VCCO power plane.

I have a considerable number of successful PCI33 and PCI66 motherboard designs under my belt, and I have had no problems routing PCI bus on layers adjacent to (and referenced to) GND plane (rather than 3.3V plane).

Generally speaking, the guidelines for parallel PCI bus layout are:

• Keep bus short, avoid long stubs.  Length-matching is not important.
• PCI_Clock traces from clock generator to each PCI device must be closely matched in length.
• If there are both removable and fixed PCI "slaves" in your system, locate a fixed PCI slave and the PCI host at opposite ends of the bus.
• Avoid gaps or discontinuities in the power or GND plane to which the bus transmission lines are "referenced".
• A single, common 3.3V supply should be used to power all PCI devices.  The supply can also be used by non-PCI devices.
• Provide 1K pullup Rs for signals which might not be well-controlled at power-up, to prevent bus contention.

There may be additional useful suggestions which I no longer remember -- it's been a while since my last parallel PCI bus design.

-- Bob Elkind

[diegoroman17]

Bob,

Thanks for you response. I am designing a prototype of PCI card for my engineering thesis. It´s posible that in a future I can sell this card.

The reason why I have isolated the source of 3.3V PCI bus of 3.3V VCCO source is that PCI Specification say 3.3V +-10% (3V to 3.6V), but the range of tolerance of SPARTAN-6 Family for 3.3V VCCO source is +5% -10% (3.0V to 3.45V). This forces me to regulate from 5V rail PCI to 3.3V +-5% for supply VCCO pins for PCI bus.

 Avoid gaps or discontinuities in the power or GND plane to which the bus transmission lines are "referenced".

Precisely at this point is to which I refer. Having two sources of 3.3V (The PCI busand regulated) to which power plane should reference my signals?

I have a considerable number of successful PCI33 and PCI66 motherboard designs under my belt, and I have had no problems routing PCI bus on layers adjacent to (and referenced to) GND plane (rather than 3.3V plane).

I understands that can reference my signals to GND plane but I have a stack up layer that not permit do it:

-Signal

-PWR

-GND

-High Speed Signal

-High Speed Signal

-GND

-PWR

-Signal

I can only route PCI signal in the top and bottom layer because Internal High Speed Signals will be ocupped for signals for DDR2. I have few experience in this designs with FPGAs. Thanks in advance for your help.

Diego Cabrera

[eteam00]

Suggestions:

• Add 2 more signal layers
• Move the DDR2 to clear room for PCI
• Move PCI pins or bus to avoid DDR2
• Change design rules to permit denser routing
• Consolidate the two 3.3V supplies into a single supply
• Be prepared for a slower PCI bus operating frequency to accommodate longer bus settling time
• Be prepared for possible EMI compliance problems

Welcome to the world of hardware engineering!  You are learning more about making tradeoffs, and deciding which tradeoffs and risks and costs you can afford.

-- Bob Elkind

[diegoroman17]

Thanks for the welcome. The hardware engineering is very exciting for me.

Consolidate the two 3.3V supplies into a single supply

I don´t understand how can be this. The one 3.3V supply is of bus PCI and the other 3.3V supply is my source regulate for VCCO...How can consolidate it? And how is the way for route it?

I can not add more layers for cost.

[eteam00]

The one 3.3V supply is of bus PCI and the other 3.3V supply is my source regulate for VCCO

Why must they be separate supplies?

-- Bob Elkind

[bassman59]

---

diegoroman17 wrote:

Bob,

Thanks for you response. I am designing a prototype of PCI card for my engineering thesis. It´s posible that in a future I can sell this card.

The reason why I have isolated the source of 3.3V PCI bus of 3.3V VCCO source is that PCI Specification say 3.3V +-10% (3V to 3.6V), but the range of tolerance of SPARTAN-6 Family for 3.3V VCCO source is +5% -10% (3.0V to 3.45V). This forces me to regulate from 5V rail PCI to 3.3V +-5% for supply VCCO pins for PCI bus.

---

You may not even find a 5V PCI slot! (And make sure your PC board is "keyed" for the allowable supply voltages.)

Last time I did a parallel PCI design, I simply connected the bus 3.3V to the FPGA. The FPGA pins can deal with it, although you should check your timing constraints so the worst-case analysis includes the -10% corner.

[diegoroman17]

Bob this is the reason why I have two 3.3V power supply in my card,

"For Spartan-6 devices, the Spartan-6 FPGA Data Sheet lists the VCCO requirement as 3.3V 

with a range of -10% to +5% (3.0V to 3.45V). It is required to regulate the VCCO voltage
because the PCI Specification specifies the PCI power rail to be 3.3V +/- 10% (3.0V to 3.6V).
The regulator must regulate to 3.3 volts to maintain compliance."

This is fragment the "Electrical Compliance" in LogiCORE™ IP Initiator/Target v4.13 for PCI™ Getting Started Guide (UG260) pag. 25

[diegoroman17]

HI,

The PCI 3.0 say that support 5V for signals is obsolet but 5V power is conserved. The pins in PCI connector for 5V power are B5, B6, A5, A8, B61, B62, A61, A62. To understand better my card that I desing I have create a block diagram. The total project is a PCI controller for laser cutting machine and the core of the card is a SPARTAN-6.

[eteam00]

I would use the PCI bus 3.3V supply for Xilinx VCCO supply.  See note (8) attached to DS162 Table 2:

For PCI systems, the transmitter and receiver should have common supplies for VCCO.

Alternatively, you can generate a new 3.3V supply for the Spartan-6 VCCO, and use the same supply for all the 3.3V devices on the board.  The result will be a single 3.3V plane instead of two, which may provide some relief for your layout problems.

PCI3.3V bus signal levels are nominally LVTTL, which is relatively insensitive to VCC differences.  The multi-point, multi-stub bus topology can results in significant reflections and overshoots.  These are addressed, in part, with clamp diodes to the VCC rail at every input/output pin.

The clamp diodes might be a problem if one bus driver is "hot" (high VCC) and another device (receiver) has a low VCC supply -- there is the potential for a (more or less) steady state clamp diode forward bias, or a high effective pin capacitance, as a result.  Conversely, the effectiveness of the PCI clamp diodes is reduced if a driver has a low 3.3V supply and the other PCI devices have a 3.3V rail which is "hot" (high).  These are the reasons for wanting a common 3.3V VCC rail for all PCI bus connections.

You must then decide what non-PCI logic or interfaces on your board might be compromised or affected by using the PCI bus 3.3V supply.  If there are potential risks, can they be eliminated from your design?

Keep in mind that you have no control over users or customers using PCI bus extender cards or bus analysers which will torture the signal integrity properties of the PCI bus further than normally expected.

Your principles are correct.  The correct design approach is to use the PCI bus 3.3V supply only for the VCCO to the IO bank dedicated exclusively to PCI bus interface, and use a separate 3.3V supply for non-PCI circuitry.

There are many tradeoffs to be made in real-world design, often between technical attributes (such as signal integrity) and production cost (additional board layers).

-- Bob Elkind