Spartan® Family FPGAs

[diegoroman17]

I'll consider your recommendation.

I am using bank 1 to ddr2 and  bank 3 to pci. these banks are on opposite sides of the FPGA and their signals do not overlap or cross.

[eteam00]

I am using bank 1 to ddr2 and  bank 3 to pci. these banks are on opposite sides of the FPGA and their signals do not overlap or cross.

Good.  Then there is no need to keep them on separate signal routing layers.

• If signals are short, then you really should not have problem using any and all layers, for either DDR2 or PCI.
• Because PCI is on card edge connector, there is advantage in first using top and bottom layers for PCI routing.
• For DDR2, the package pinout is fixed by MIG, and the "escape" pattern from the BGA will be your toughest problem.

-- Bob Elkind

[diegoroman17]

I have a question...Is posible use the PCI 3.3V voltage rail to supply VAUX pins? this would be very helpful. I am using PCI 3.3V voltage rail to supply XCF16PVO48C VCCO pins.

[eteam00]

Did you mean VCCAUX pins?  Or VAUX pins?

You should search the datasheet document for instances of VCCAUX to answer your question.

-- Bob Elkind

[diegoroman17]

Sorry. I refer to VCCAUX. In the datasheet recommend min 3.15V and max 3.45V to VCCAUX, but PCI 3.3V rail range is min 3.0V and max 3.6V. Can it difference to affect my FPGA?

[eteam00]

This is a very good question.

VCCAUX and VCCO have the same Maximum and Recommended ratings in DS162 Table 1 and 2.

Perhaps this is a question for Austin Lesea, or possibly a webcase.

-- Bob Elkind

[diegoroman17]

Hi Bob,

I contact with Austin and he explain me that is posible use the same 3.3V PCI to supply VCCO and VCCAUX but is recommend use a regulator to maintain the voltage in 5%. For reason of cost I decide not use extra regulators. Now you recommend me above  provide 1K pullup Rs for signals which might not be well-controlled at power-up, to prevent bus contention...What is this signals? I have not heard about pull-ups in pci.

[eteam00]

Now you recommend me above  provide 1K pullup Rs for signals which might not be well-controlled at power-up, to prevent bus contention...What is this signals? I have not heard about pull-ups in pci.

When I wrote this (see post #2 in this thread), I did not yet know whether you are designing a PCI target board or a PCI host interface.  The pullups would be appropriate for a host design, but not a target board design.

-- Bob Elkind

[diegoroman17]

Bob can you recommend me a number and value of disacouple capacitor to PCI connector and the distance max of capacitor to connector PCI?

I not understand if is necessary to place capacitors near of PCI connector or only is necesary to place capacitor near FPGA.

[eteam00]

Diego, there is no single (exclusive) "right" solution for power supply bypassing and decoupling.  The parts which I would select, for example, may be difficult (or expensive) to obtain in your home country.

In my latest designs, I use three different multi-layer ceramic capacitors for power supply decoupling and bypassing:

• 0402 1.0uF, one of these is placed as close as possible to each power supply pin.
• 0805 10uF 16V, for bulk decoupling, distributed evenly in the board area where the power supply is used
• 0805 4.7uF 25V, for bulk decoupling of power supplies which are nominally 12V or higher

I generally do not use tantalum, aluminum, or 'special polymer' electrolytic capacitors in my designs, primarily because my (typcally low-current) designs generally do not need them.

-- Bob Elkind