Spartan® Family FPGAs

[diegoroman17]

It is a good idea but for my prototype I will try to use the 3.3V PCI power rail directly for reason of cost and minus complexity. This power rail can give 7 Amp.

[eteam00]

I need two Power layers and two GND layers or one power layer and one GND layer?

One GND plane and one (split) POWER plane.  Two layers, total.

For DDR2 signals:

-Trace width characteristic impedance driven width min 50Ohm preferred 50Ohm and max 50Ohm.

You have the option (selectable in MIG) for 50-ohm, 75-ohm, or 150-ohm impedance.  When you choose your board stackup, you can select use the minimum trace width to select a preferred characteristic impedance.  For example, if mimum trace width is .14mm, and a minimum width trace has a characteristic impedance of 75-ohms, then you should use minimum width traces.   In MIG, select 75-ohm (nominal) impedance for RTT/ODT to match the characteristic impedance of the traces.

-- Bob Elkind

[diegoroman17]

Ok, If I select 1 layer to power plane, 1 layer to GND plane and 6 layers to signals. which is the stack-up layer?which is the thickness of prepreg and core?

I have a selected in MIG 50 Ohm and In Altium trace width I have 50 Ohm too. Is it correct?

In Altium I have of 60 Ohm to 100 Ohm preferred 75 Ohm for PCI signals only, Is it correct?

Spartan-6 FPGA Memory Controller User Guide (UG388) say that all the DDR2 signals must be referenced to GND Plane, don't to Power plane. Is it posible with only one GND plane? 

[eteam00]

Ok, If I select 1 layer to power plane, 1 layer to GND plane and 6 layers to signals. which is the stack-up layer?

which is the thickness of prepreg and core?

You do not yet know that you will need 6 signal layers.  When and if you do determine this, suggest you contact the board fabrication house for recommended stackup information.

• Tell board house desired number of signal and plane layers and desired single-ended and differential impedances, etc.
  
• Board house responds with recommended stackup, trace widths, target nominal impedances, dielectric thicknesses, etc.

I have a selected in MIG 50 Ohm and In Altium trace width I have 50 Ohm too. Is it correct?

See my previous post.  If your board design succeeds, it is correct.  There may be more than one correct answer.

In Altium I have of 60 Ohm to 100 Ohm preferred 75 Ohm for PCI signals only, Is it correct?

I have forgotten if there is a specified or recommended characteristic impedance for PCI bus signals.  If there is no standard or recommendation, you may simplify your design by using the same target impedance for all (or almost all) single-ended signal traces on your board.

Spartan-6 FPGA Memory Controller User Guide (UG388) say that all the DDR2 signals must be referenced to GND Plane, don't to Power plane. Is it posible with only one GND plane?

In my own designs, I have referenced DDR/2/3 interconnect to both VCC (1.8V in DDR2) and GND.

-- Bob Elkind

[diegoroman17]

You do not yet know that you will need 6 signal layers.  When and if you do determine this, suggest you contact the board fabrication house for recommended stackup information.

I have contacted with several houses of fabrication of PCBs but all told I have to send the gerber file and  they no give me the information over thickness, width trace, etc. 

You know some house manufacturing and assembly of PCBs which can coordinatethis information?

[eteam00]

I have contacted with several houses of fabrication of PCBs but all told I have to send the gerber file and  they no give me the information over thickness, width trace, etc.

I have received excellent service from Genaro Rodriguez <Genaror@protoexpress.com>, I use them for prototype volumes.  I have no financial realtionship with them, other than being a satisfied customer.

-- Bob Elkind

[diegoroman17]

I have communicate with Genaro Rodriguez he is not available but other engineer respond me. He say that I have to dimension stack-up layers. They readjusted the prepreg thickness to comply with impedance requirements but this will make it in the manufacturing process after I give them the gerber file.

You recommend me 2 power planes but I don´t know how many layers to signals need and I don´t know how stack its layers?

[eteam00]

You recommend me 2 power planes but I don´t know how many layers to signals need and I don´t know how stack its layers?

My guess is 4 signal layers, but I am not the board designer or the layout designer.  So my guess is just a guess.

Suggest you plan on the following:

sig1

sig2

PWR

sig3

sig4

GND

sig5

sig6

• Do not use layers sig3 and, sig4 unless absolutely necessary.
• If you end up not needing sig3 and, sig4 layers,  then delete them.

Ask the board fab house if this is a reasonable (low-cost) stackup for an 8-layer board.  If it is not a reasonable stackup, they should suggest an alternate with 2 planes and 6 signal layers.

-- Bob Elkind

[diegoroman17]

Do you think if done with 6 layer:

-signal

-GND

-signal

-signal

-split power plane

signal

The two internal signal layers to route signals DDR2 and top and bottom signal layers to PCI signals. you think of my idea?

[eteam00]

Do you think if done with 6 layer:

-signal

-GND

-signal

-signal

-split power plane

-signal

Ask the board fab house.  They may say that S | S | P | G | S | S is easier to fab.

The two internal signal layers to route signals DDR2 and top and bottom signal layers to PCI signals. you think of my idea?

You will probably need more than 2 layers to connect DDR2.  DDR2 needs 1.8V IO bank, PCI needs 3.3V IO bank.  If these two sets of signals overlap, you have done something wrong.

-- Bob Elkind