10-08-2007 04:31 AM
I am designing a Spartan3E board with a DDR SDRAM. The DDR is,
similarly as in Spartan3E Starter Kit but connected to bank1 (2.5V
with 1.25V reference) for lower routing delay.
The Spartan3E SK the clock fedback (used by OPB_DDR) is confusing me:
On S3Estarter, it goes to another bank (bank 0). They wrote in the
The differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O
Bank 0 to have best access to one of the FPGA's Digital Clock Managers
(DCMs). This path is required when using the MicroBlaze OPB DDR controller.
Of course, here the signal standard won't match (3.3V instead of 2.5V)
and they did not connect VREF to in this bank. Does this matter or not?
In the banks with low routing delay (1 and 3), there are no global
clocks, only LH and RH clocks. Will they work too?