Spartan® Family FPGAs

[eschabor]

Bob, your analysis is good - but I think there's two of us providing answers and no further questions from Pieter!

Stephen

[eteam00]

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eschabor wrote:

Bob, your analysis is good - but I think there's two of us providing answers and no further questions from Pieter!

Stephen

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Stephen, I concur with your analysis of the analyses!

-- Bob Elkind

[rifo]

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eschabor wrote:

"16bit DDR2 and the MCB interface is 32bit. So should be perfect I think."

No, DDR2 has a minimum burst of 4, so the minimum efficient transfer size is 64 bits.  The use of 32 bit transfers immediately throws away 50% of your bandwidth.

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Hello,

Shouldn't the internal mechanics of the MCB handle this so that bandwidth is not wasted? For example if I completely  fill a MCB port Fifo (configured in 32 bit) do I automatically lose half of my bandwidth?

thanks a lot for your help

rifo

[eteam00]

@rifo

Shouldn't the internal mechanics of the MCB handle this so that bandwidth is not wasted? For example if I completely  fill a MCB port Fifo (configured in 32 bit) do I automatically lose half of my bandwidth?

For example, Stephen (eschabor) is saying:  'For maximum efficiency, request data transactions which are a multiple of the fundamental DRAM transaction (e.g. 64 bits in the case or 16-bit DDR2 with DRAM burst length of 4).'

Even if you fill a MCB port FIFO, you must tell the MCB how much of the FIFO data to use for each memory transaction from one of the MCB user (fabric) ports.  You explicitly convey this information by way of the pX_cmd_bl[5:0] user-interface MCB signal port.  See UG388, seach for 'cmd_bl' for additional information.

Make sure you understand the difference between user-port 'burst length' (how many FIFO words are to be read or written) and DRAM device-level 'burst length'.  These are two very different attributes which sound deceptively alike.  One is described in UG388 as a part of the MCB interface.  The other is described in the DRAM device datasheet.

-- Bob Elkind

[rifo]

thanks a lot Bob,

I misunderstood what Stephen was sayin but it's clear now.

[rabidfruitbat]

Hi all,

I am testing a Spartan6 design using x16 DDR2 SDRAM and it appears to have very poor performance.

I'm issuing write command  bursts 16 x 32bit data word and read commands of 16 x 32bit words. My data access pattern is sequential.  i.e. I'm using the SDRAM as a really deep FIFO, so reads and writes are to different pages.  

The sustained data throughput is 43% of peak data throughput. i.e. for 400MHz DDR I can not read and write data at 100MHz x 32 bits.

This seems to be very poor performance.

Does anyone have any idea if this is typical performance for the MCB? Do I have to change my interface to use the 64bit or 128bit interfaces to the MCB?  Is there any other way to improve this?

Best Regards, Thomas D.

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[jliu83]

I'd like to see if anyone out there has some measurable data on this.

For example, on a single DDR2 16bit width chip, using a 32 bit write MCB port.  If I fill the fifo of the MCB write port and send a command to the MCB with a user burst length of 64 (the max length), then I automatically lose half of my bandwidth on that transaction based solely on my configured port width?  It sounds like a terrible design if this is true!  I would think that since the transaction is on a continuous stretch of address, the MCB controller would optimize it so that the DRAM bursts would not waste bandwidth.

Did I miss understood something, or was the optimization implied in the response?

I have having trouble achieving write bandwith (read is perfectly fine).  Has anyone seen an improvement in performance by increasing the port clocks (ie. p0_wr_clk, p1_rd_clk ... etc).

Thanks,

-J

[eteam00]

J,

Please start a new thread for this discussion subject.

-- Bob Elkind

[jliu83]

Done

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-MCB-Performance/td-p/244006

-J