Right solution for capacitor selection - using PDN calculation and/or simulation.
Understanding the underlying concepts, theory, and practical details is very useful. On the other hand, if all the theory and science can be summarised in what some people call "rules of thumb", this makes life simpler for many designers.
For example:
When you drive your auto to the filling station, do you check the compression of your engine, the atmospheric pressure, the ambient humidity and temperature, and the ignition timing of your auto's spark generator before selecting which octane rating of petrol to purchase? Or do you simply accept the manufacturer's recommendation for octane rating 87, as a reasonable and practical summation of expert analysis and calculation which has been done on your behalf?
The Xilinx board design recommendations for decoupling caps are intended to be a reasonable and practical summation of expert analysis and calculation. Such summations are possible and practical because the problem of decoupling capacitor selection isn't all that difficult. The advent of high-quality MLCC surface mount capacitors, replacing leaded ceramic and aluminum capacitors, has greatly simplified the task of providing a competent solution.
See this link for example
The linked white paper is excellent. The attention given to layout and board stack-up considerations is very helpful.
Selection of caps not only searching cheap parts at Digi.
You have over-simplified, Victor. Read my comments again. X5R capacitors are not the cheapest parts -- they are the high-quality fine-tolerance stable parts. The cheapest X5R caps (from a reputable distributor and manufacturer) are not the cheapest caps.
Good PDN design provide low power plane impedanse at given frequency band.
Unfortunatelly Xilinx not provide any PDN calculators :(
Providing a reliable and cost-effective solution -- for capacitor selection -- is not that difficult, and the guidance provided by Xilinx is in the form of easy-to-follow instructions. I have my own "rule of thumb" practice which is also reliable and cost-effective. My approach is not the only correct one, and the success of my approach does not mean that the Xilinx recommendations are flawed -- they are not.
One of the purposes of this thread is to reduce level of fear, uncertainty, doubt, and anxiety of FPGA/board designers where capacitor selection and layout decisions must be made.
It is one thing to say 'here is a white paper on the underlying principles and considerations, in case you are interested'.
It is quite another matter to say (or imply) 'nothing you have read from these folks is safe and reliable, the only proper guidance is from this PDN calculator'. This would be both untrue and counter-productive.
-- Bob Elkind
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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
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