Spartan® Family FPGAs

[giacciocl]

Hello Everybody,

I need your help for debugging a strange behavior on ODDR2. I'm using a LX16 Spartan6 and the ISE13.3.

I have instantiated an ODDR2 in order to drive an output (see the RTL on the following).

    IP2Card_DATs : ODDR2
  generic map(
      DDR_ALIGNMENT => "C0",
      INIT          => '1',
      SRTYPE        => "ASYNC"
      )
  port map(
      Q  => IP2Card_DATs_line_out,
      C0 => IP_Clk,
      C1 => IP_Clk_180,
      CE => Vdd,
      D0 => IP2Card_DATs_line_D1_in,
      D1 => IP2Card_DATs_line_D2_in,
      R  => Reset,
      S  => gnd
    );
 

When the IP_Clk is 25 MHz I correctly see the start bit (a '0' bit for starting the payload communication), sent through Q pin. On the other hand, when the IP_Clk frequency rise up to 50 MHz, I can see two start bits sent through the ODDR2 output pin. This problem appears only on the start bit and only at 50 MHz. The payload in both 25 and 50 MHz frequency is correct.

Please, could someone help me?

Thanks in advanced

Claudio

[eteam00]

When the IP_Clk is 25 MHz I correctly see the start bit (a '0' bit for starting the payload communication), sent through Q pin. On the other hand, when the IP_Clk frequency rise up to 50 MHz, I can see two start bits sent through the ODDR2 output pin. This problem appears only on the start bit and only at 50 MHz. The payload in both 25 and 50 MHz frequency is correct.

• Is this "problem" in simulation results, or in actual hardware?
• Do the ODDR2 block inputs suggest the ODDR2 block is not functioning correctly, or that the input signals are incorrect?

-- Bob Elkind

[giacciocl]

Hi Bob,

sorry for e late reply.

The problem arisen on the hardware, the simulation works properly.

The input signals are correctly applied, the start bit is driven from a state machine and it is tie low just for one clock cycle. So it is very strange that after the ODDR2 remains on the bus for twice.

What do you suggest? Could the problem related to ODDR2 wrong behavior? What the next?

Thanks Claudio

[eteam00]

The input signals are correctly applied, the start bit is driven from a state machine and it is tie low just for one clock cycle. So it is very strange that after the ODDR2 remains on the bus for twice.

Question: How do you verify that inputs to ODDR2 are correct in actual hardware?

-- Bob Elkind

[giacciocl]

Hi Bob,

thank you for prompt replay.

I have probed the ODDR2 input.

Anyway tomorrow I have another test session in Lab.

I'll save the waveform in order to post it.

Question: Could this problem related to C0 DDR Alignment?Do you suggest other DDR alignment?

Thanks

 Claudio

[eteam00]

Question: Could this problem related to C0 DDR Alignment?

If the ODDR2 D inputs are both generated on the rising edge of the C0 clock (e.g. by a state machine using C0 clock), C0 alignment is correct.

-- Bob Elkind

[giacciocl]

Thank you Bob.

So you are not aware of any problems related to DDR alignment. This is a good news for me.

Tomorrow I'll perform new tests. I'll keep you update.

Claudio

[eteam00]

So you are not aware of any problems related to DDR alignment.

You have not posted any of your code, particularly the code which generates data inputs to ODDR2 block, so my affirmation is limited to the ODDR2 block capabilities.

-- Bob Elkind

[giacciocl]

Hi Bob,

I've just found out a problem on the ODDR2 input signals. I have to investigate regarding it.

I'm generating a new bitstream in which probing the State machine stimulus in order to deep understand the scenario.

I thing the investigation will be complete tomorrow and I'll post the results.

Thank you so much for you support. I'll keep you update

Claudio

[giacciocl]

Hi Bob,

sorry for a late replay.

After a deeper analysis I found out timing problem related to the ODDR2 input signals.

Sorry for the mistake. Anyway thank you so much for your help. Your help was very useful for my debug

Keep in touch

 Claudio