Hi mrflibble,
Awesome! I'm glad you got it working.
I wanted to be able to change header fields from packet to packet, so I added code to my state machine to do it:
module ip_header_checksum(
input clk,
output wire [15:0] checksum,
input wire [31:0] header,
input wire reset
);
reg [31:0] checksum_int;
reg [2:0] header_count;
always @(posedge clk)
if (reset) begin
checksum_int <= 0;
header_count <= 0;
end
else
if (header_count != 5)
begin
header_count <= header_count + 1'b1;
checksum_int <= checksum_int + header[15:0] + header[31:16];
end
assign checksum = ~(checksum_int[31:16] + checksum_int[15:0]);
endmodule
Then in the packet generator code:
reg [31:0] header_checksum_input;
wire [31:0] header_checksum;
reg header_checksum_reset;
ip_header_checksum ip_header_checksum_1 ( .clk(mac_clk), .checksum(header_checksum), .header(header_checksum_input), .reset(header_checksum_reset));
// Then within the packet generation FSM, before starting to send
// anything out, generate the checksum:
0: header_checksum_reset <= 1;
1: header_checksum_reset <= 0;
2: header_checksum_input <= {16'h4500, ETHERNET_LENGTH[15:0]};
3: header_checksum_input <= {8'd0, ip_identification, 3'b000, FRAG_1[12:0]};
4: header_checksum_input <= {16'h4011, 16'h0000};
5: header_checksum_input <= SRC_IP;
// etc.
Then when you start sending the packet to the MAC, substitute in the checksum at the appropriate place. I ended up doing it word-by-word rather than using a loop like I did in the example. It's a bit more code, but it made it a lot easier to send a series of different packets in sequence! Using Verilog tasks reduced the code to this:
71: begin
mac_flags <= 4'b0000;
transmit_header({DST_MAC[15:0], SRC_MAC[47:32]});
end
72: transmit_header(SRC_MAC[31:0]);
73: transmit_header(32'h0800_4500);
74: transmit_header({ETHERNET_LENGTH[15:0], 8'd0, ip_identification});
75: transmit_header({3'b000, FRAG_5[12:0], 16'h4011});76: transmit_header({header_checksum, SRC_IP[31:16]}); // IP checksum (4), srcip (4)
// etc.
task transmit_header;
input [31:0] header;
begin
header_data <= header;
packet_gen_state <= packet_gen_state + 1'b1;
end
endtask
From memory there was something wrong with the synchronisation of reset signals to the different clock domains. It didn't seem to cause any problems in such a simple design, but you should fix it for completeness (I did in my ongoing work project, but haven't updated the extracted example).
Thanks for the information on the Spartan-6 speed grade! The manual is pretty spotty, and I'm not really sure why I thought it was a -3. I'll update the information on my site.
