Spartan® Family FPGAs

[jmm385]

If i read the Spartan3 datasheet correct, there is an internal silicon oscillator in each Spartan3 that can be configured to be the CCLK clock for configuring the FPGA in master serial mode, and there is a PERSIST option that can keep the clock on after configuration.  My question is, can I use this clock inside the FPGA as a master clock for the FPGA and the board?  I have an application where I want as few parts as possible on the board, and I don't really care what the master clock frequency is, as long as it is a 1-50MHz clock.
To use CCLK would I have to have a PCB trace connecting the CCLK output pin to another FPGA I/O pin or can I conenct to it internally?  I did not see a schematic library part that has CCLK.  Is there any way to do this?
Thank you,
-J

[gszakacs]

There were earlier parts that had the ability to use the internally generated clocks.  However IIRC Spartan3 does not have this feature.  Also the PERSIST option does not do what you want.  It may cause the CCLK pin to keep its I/O standard after configuration, but won't actually keep the oscillator running.

[jmm385]

Thanks for the information.   What does IIRC mean?

[mcgovern]

The Persist options allows the CCLK pin to remain active but only as part of a configuration interface. This allows you to access Configuration Memeory and Carry out operations such as Readback of the config data. You can not access this clock in the Fabric however.

-P

[gszakacs]

IIRC:  If I Recall/Remember Correctly

Net jargon for non-typists.  If you use newsgroups you run into a lot of these :)