06-02-2012 06:17 PM - edited 06-02-2012 06:19 PM
Im looking at the page 26, of UG380, Slave serial configuration schematics.
You can notice a red point on the JTAG connector, that is VREF. So, i connect it to the pin A12 of my device, which has a VREF functionality.
But, it is unclear why there is Vcc_Aux pointing on to the VREF pin of JTAG connector as well?
In my case im using only 3.3v peripherals, and VCC_AUX is tied to 3.3v as well.
So, do i need to just connect VREF pin of JTAG connector to A12 of my device and thats it?
Or, do i need to connect both VREF of my JTAG connector AND the A12 pin of the device to 3.3v rail?
Solved! Go to Solution.
06-02-2012 06:34 PM - edited 06-02-2012 06:37 PM
Im also looking at this post by eteam00 :
And from here it seems to me that the JTAG connector should be connected to VCCAUX, or in my case, just to 3.3v Rail?
Now, all i have to do now, is to tie A12 to 3.3v rail as well?
What about other pins with VREF functionality? Do i need to tie all of them to 3.3v, or just one of them?
06-02-2012 07:08 PM
You can find more information in the Configuration User Guide for each FPGA family.
Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
06-02-2012 07:09 PM - edited 06-02-2012 07:33 PM
In the context of UG380, VREF is for the attached JTAG controller (for example, a USB Platform Cable). It tells the JTAG controller what logic swing the JTAG (or TAP) target device(s) is using.
For example, with Spartan-6 devices the JTAG interface pins are powered with VCCAUX, which can be either 2.5V or 3.3V. So UG380 directs you to connect the VCCAUX supply voltage to the JTAG Cable Header VREF pin.
The VREF pins on the FPGA are for a completely different use and application context. Certain single-ended IO standards require a logic switch threshold reference voltage for input signals. It is for these IO Standards that the VREF pins are provided and used. See DS162 Table 7 for a list of the IO standards which require the use of the VREF pins, and Table 9 for input level specifications referenced to VREF.
In sum, the use of the FPGA VREF pins has no bearing on or relationship to the JTAG header VREF pin. None!
-- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
06-02-2012 07:24 PM
yeah right, i also saw from UG394 that its used for HSTL/SSTL.
so i guess, in my case i'll just leave them unconnected or use for other purposes.