03-12-2010 12:05 PM
I have taken it as a programming habbit to write my modules in the following manner:
always @(negedge rst_n or posedge clk) begin
if(rst_n == 0) begin
end else begin
Now, Assuming there is no external device to do this resetting initially, is there a way to start the system in reset mode ?
03-12-2010 04:58 PM
One way of doing it is to connect "rst_n" to the 'locked" output of the DCM, if you use it for the "clk".
I understand you're using Spartan. In Virtex-5 you could've used EOS output of the STARTUP_VIRTEX5 primitive. EOS is asserted at the end of the FPGA configuration.
Hope that helps,
03-12-2010 08:35 PM
For now, i am not using the DCM, but this may be a very good idea, i will try it and see what happens.
Frankly, i was thinking of finding a way to connect the DONE pin to inside the FPGA, dunno if that is even possible
03-13-2010 01:32 AM
I was doing some reading, and i found that there is a global set/reset GSR provided.
i looked in the code provided by xilinx, and i found that it is instantiated as follows:
tri0 GSR = glbl.GSR;
I tried it and it didn't synthesize complaining that glbl doesn't exist.
i instantiated the glbl module, but still xilinx couldn't find it, even though i am using some of xilinx's primitives and they used and it is compiled correctly.
Is there anything i am missing in using this module ?