Spartan® Family FPGAs

[jess4763]

Hello,

My circuit drives one LVCMOS33 I/O pin low for each LED cathode in set of 38 LEDs. The anode of each LED is connected through a current limiting resistor to the 3.3V rail. I need to decide how low I can set my current limiting resistor and stay within the limits of the FPGA.

How much current can each I/O pin sink?

How much total current can all 38 I/O pins sink simultaneously?

Thanks!

[eteam00]

Check the IBIS models for V vs. I curves.

If you need precise control over LED current, consider using external constant current sources which are turned on/off under FPGA control.  A constant current source can be little more than a transistor and a few resistors.

-- Bob Elkind

[jess4763]

Hello Bob,

I'm not using the FPGA I/O to control current, the precision of my limiting resistors is sufficient for that purpose. The I/O pin just pulls the circuit to ground and sinks whatever current the resistor sets it to.

My concern is sinking too much current through each I/O pin. There is a clamp current spec of +/- 100mA on page 56 of the ds099 datasheet (http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf), however it seems to me that 100mA sink current through 38 I/Os would be excessive.

Can you clarify?

Thanks

[eteam00]

My concern is sinking too much current through each I/O pin. There is a clamp current spec of +/- 100mA on page 56 of the ds099 datasheet (http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf), however it seems to me that 100mA sink current through 38 I/Os would be excessive.

Are you sure the clamp current spec is informative in this application?

• There is an over-riding operating conditions spec of 125 deg C die temperature.

• Each LVCMOS33/LVTTL output can sink at 24mA @0.4V.  Assuming 38 pins all active simultaneously and persistently, this represents roughly steady state 365mW dissipation internally.

The IBIS model should guide you to I vs. V characteristics beyond 24mA sink level.

How much current (peak/average) are you interested in sinking, per pin?

-- Bob Elkind

[austin · Accepted solution]

Further,

The 100 mA per bank is the source or sink ABOVE Vcco, or BELOW ground, to prevent SRC crowbar, or destructive LATCHUP (200 mA total for the device, no more than 100 mA per IO bank.

It has nothing to do with designing drivers to LEDs.

The IBIS models will show you exactly what a driver will drive, when set for a specific standard.  For example, the 24 mA driver is gauranted for a minimum of 24 mA, sink or source, at valid logic high and low levels, over all process, voltage, and temperature conditions.  Is it able to drive more than 24 mA?  Absolutely:  it may drive as much as 120 mA if you force it to.  So, don't force it to drive any more than what it is gauranteed to do.  So, if you choose a 8 mA driver, do not use it to drive more than 8 mA!  If you choose a 12 mA driver, do not use it to drive more than 12 mA.  And so on, and so forth.

[jess4763]

Bob/Austin,

This answers my question.

Thanks for your time!