Spartan® Family FPGAs

[yase]

Hi All,

I have recently brought a Spartan-3 FPGA Board with a DDR SODIMM interface. I am trying to use Xilinx MIG to controll the DDR memory.

The problem is, the ddr pins on the board that I have purchased does not comply with the I/O banking rules of the MIG (top and bottom or left and right). Will it be ok, if I just disregard the I/O Banking rules of the MIG and modified the ucf to match the pin-out of my board?

Also, is there any example for vhdl user application for the Spartan DDR memory controller generated by MIG 1.72. I still find it a bit hard to write the user application  ;-( .

Thank you very much!

Regards,
ymm

[jacobusn]

Hi,

No you can't just change the pin-out. The Spartan-3 controllers generated by MIG uses a template router and if you change the outputs the routing delays won't be correct anymore. You can get more information here and here:

As for a example vhdl user application, someone else might be able to help you with that.

Jaco

[yase]

Hi,

Thank for the response.

I realised that the hardware that im using utilized the top and left bank for the DDR data pins. Xilinx MIG only generates core for top/bottom or left/right banks. I am wondering if there is any patch or way to make xilinx MIG to generate ucf for top/left bank?

Thank you very much.

ymm