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Visitor
jackseiko
Posts: 8
Registered: ‎04-22-2009
0
Accepted Solution

a simple VHDL code, plz help!!

[ Edited ]

Hi, I need to generate Strobe (S) signal from my Data (D) signal as the figure shows. 

 

 

 

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 

D-S encoding

 

Message Edited by jackseiko on 05-29-2009 12:46 AM
Super Contributor
bobster_the_lobster
Posts: 210
Registered: ‎07-15-2008
0

Re: a simple VHDL code, plz help!!

I can't really see how your strobe related to your data can you exsplain?

 

Kind Regards Bobster

Visitor
jackseiko
Posts: 8
Registered: ‎04-22-2009
0

Re: a simple VHDL code, plz help!!

I have solved it thanks for your reply :)
Expert Contributor
eilert
Posts: 2,064
Registered: ‎08-14-2007
0

Re: a simple VHDL code, plz help!!

Hi Jack,

The problem is quite simple.

You are doing everything combinatorical.

 

Instead your Strobe signal has also to be generated inside a synchronous process.

You already created a synchronous delayed signal "a" from the Input "diffout".

 

For a first try:

Move your assignments for xorout, strobe_signal and diffstrobe into your process and see what happens.

I'm quite sure that this isn't the final solution, but at least your diffstrobe signal will not be shorter than a clock period anymore.

Of course, now you have to deal with pipelining problems. Just look at the RTL-Schematic to get an idea of your synthesis result.

 

 Now rethink your approach and improve your coding.

 

Have a nice simulation

  Eilert

 

Expert Contributor
bassman59
Posts: 4,679
Registered: ‎02-25-2008
0

Re: a simple VHDL code, plz help!!


jackseiko wrote:
I have solved it thanks for your reply :)

Why don't you be a good sport and explain to us what you did to solve the problem? It's only fair.

 

-a


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