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kurtwick
Posts: 1
Registered: ‎10-15-2008
0

asynchronous reset implementation with latch instaed of register

Hi,

 

I have a very basic question about the implementation of Verilog statements into RTL.  Specifically, I am wondering how asynchronous resets are implemented.

 

In my example, I have a counter. When it receives a reset signal I want to store its count value (in a separate register) and reset the counter.

 

I am using a Digilent BASYS board with a Spartan 3E and the module below works fine when actually testing it and does exactly what it is supposed to do: it assigns count_int (internal counts) to count_final at the negative edge of reset and resets the counter.

 
 

module BCounterwAsyncWorks(trig, reset, count_int, count_final);

    input trig;

    input reset;

    output reg[3:0] count_int = 0;

    output reg [3:0] count_final = 0;

           

            always@(posedge trig or negedge reset) begin

                        if( reset == 0) begin

                                    count_int <= 0;

                        end

                        else begin

                                    count_int <= count_int + 1;

                        end                              

            end

 

            always@( negedge reset) begin

                                    count_final <= count_int;

                                    end

endmodule

 

Here is what is puzzling me: By making one small change to the code above, it no longer works, i.e., count final always remains at 0:  See below:

 

module BCounterwAsyncAlone(trig, reset, count_int, count_final);

    input trig;

    input reset;

    output reg[3:0] count_int = 0;

    output reg [3:0] count_final = 0;

           

            always@(posedge trig or negedge reset) begin

                        if( reset == 0) begin

                                    count_int <= 0;

                                    count_final <= count_int;  //CHANGE / ADDITION

                        end

                        else begin

                                    count_int <= count_int + 1;

                        end                              

            end

endmodule

 

Note, the only thing I did was to move the “count_final <= count_int;” into the previous always block.

 

First, when I tested the actual hardware circuit, I made sure that the reset and trig pulses NEVER overlapped.  I understand that for some conditions of overlap, for example, if trig goes LO when reset is 0, the output count_final will be 0.  So let’s not consider these cases and only try to discuss only what happens when reset and trig are non-overlapping.

 

Second, when I create a timing diagram of the circuit in the Xilinx ISE simulator, it does exactly what I expect it to do, i.e., count_final always is identical to count_int at the reset.

 

Third, and most interestingly, I did check the RTL implementation of the circuit.  In the first module shown above, the one that works, the non-blocking assignment of the count_int to count_final is (not surprisingly) carried out using a D-Type flip-flop, i.e. FD.  (Sorry wasn't able to post schematic below.)

 

In the module that does not work, the second one, the non-blocking assignment of  count_final <= count_int; uses an LD, a transparent latch with a negated clock input, i.e., it sees a positive edge input.  Since this type of latch will only hold its value on the negative edge, it makes sense why the hardware version never worked.

 

So what I don’t understand, why would does the Xilinx Webpack ISE implement the second Verilog module using a transparent latch?  Can anyone enlighten me on this?  Thanks for your help,

Kurt