Hi
I'm using the XuLA200 devboard with a XC3S200A FPGA
But I have some questions regarding the behavior of the JTAG Pins during the test-logic-reset state.
Given the condition:
- FPGA is a Spartan3A
- TAP ist already in test-logic-reset state
- TMS is pulled high
- TCK keeps being toggled
In what state will be the TDO pin?
- High-Z?
- the state before test-logic-reset?
- Bypass from TDI?
- or undefined?
Does the TAP react to data on the TDI-pin during test-logic-reset state or does it ignore all incomming signals on TDI?
I've read that TMS and TDI are only sampled during the rising edge of TCK.
Does that mean, that you could keep toogling the TMS and TDI pins as long as TCK is held low?
Background:
I want to use the XuLA-200 board in bigger projectboard.
The XuLA has a build in PIC controller for programming the FPGA via JTAG
This PIC has an open firmware and only two free GPIO left.
I have to programm several other components (via I2C, SPI and JTAG) on the board.
But I don't want to add half a dozen diferent programming interfaces on the board.
And I also don't want to use half a dozen different programming cables for the projekt.
So my idea was to 'mis'use some pins of the PIC-JTAG-interface for other functions
while the FPGA-TAP-controller is in a passive state (test-logic-reset)
Thanks so far
cu
Hauke
