Yes, sorry for not mentioning the FPGA. It's a Spartan-6 XC6SLX45T.
-- ethernet PLL instantiation
ethPLL_1: ethPLL
port map (
ClkInxCI => Clk100MxC,
ClkOutxCO => Clk125MxC,
ResetxRI => ResetxR,
LockedxSO => EthPllLockedxS);
-- Clock forwarding circuit using the double data-rate register
-- Spartan-3E/3A/6
-- Xilinx HDL Language Template, version 13.2
ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => GmiiGTxClkxCO, -- 1-bit output data
C0 => Clk125MxC, -- 1-bit clock input
C1 => not Clk125MxC, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => ResetxR,-- 1-bit reset input
S => '0' -- 1-bit set input
);
So here is the code that instantiates the ODDR2. ethPLL takes 100MHz and produces 125MHz that is used both internally to clock the ethernetTx.vhd block (look below) and externally to the 88E1111 Marvell PHY IC. So I'm using the ODDR2 and the GmiiGTxClkxCO goes directly to the output pin. The internal block uses the Clk125MxC signal (Perhaps this is my mistake? I don't know...)
The Clk100MxC clock comes from another PLL which previously converts the input 200MHz diff oscillator signal to some other useful frequencies (actually I am using an SDRAM memory controller that needs 800MHz clock). The reason that I don't use only one PLL is that I cannot create the desired 125MHz and the 800MHz from the same primitive.
Now, regarding my other concern. Here is the ethernetTx block that sends ethernet frames.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.multiTouchPkg.all;
use work.crc32Pkg.all;
entity ethernetTx is
port (
-- Clock and Reset signals
ClockxCI : in std_logic; -- Input clock
ResetxRBI : in std_logic; -- Active low reset
-- Status signals
BusyxSO : out std_logic; -- Asserted when TX is in progress
-- Ethernet TX FIFO Read Interface
FifoDataOutxDI : in std_logic_vector(7 downto 0); -- Data from the FIFO
FifoEmptyxSI : in std_logic; -- Empty signal
FifoRdEnxSO : out std_logic; -- Read enable signal
FifoRdCntxDI : in std_logic_vector(11 downto 0); -- Read data counter
-- Ethernet PHY Tx Interface
GmiiGTxClkxCI : in std_logic; -- TX clock 125MHz
GmiiTxEnxSO : out std_logic; -- TX enable
GmiiTxErxSO : out std_logic; -- TX error
GmiiTxDataxDO : out std_logic_vector(7 downto 0) -- TX data
);
end ethernetTx;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture behavioral of ethernetTx is
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
component crcGenerator
port (
ClockxCI : in std_logic;
ResetxRBI : in std_logic;
NewFramexSI : in std_logic;
DataInxDI : in std_logic_vector(7 downto 0);
DataValidxSI : in std_logic;
EndOfFramexSI : in std_logic;
CrcxDO : out std_logic_vector(31 downto 0);
CrcValidxSO : out std_logic);
end component;
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type state is (RST, IDLE, ETH_PRE, ETH_HEADER, IP_HEADER, UDP_HEADER, DATA, CRC, ETH_EXT);
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Clock and reset signals
signal Clock125xC : std_logic; -- 125MHz clock from the tranceiver
signal ResetxRB : std_logic; -- active low reset signal
signal StatexDP, StatexDN : state := RST;
-- Transmit byte counter that is reset on each state transition. Max value is
-- the max number of user data bytes allowed
signal InStateCountxDP, InStateCountxDN : natural range 0 to MAX_UDP_BYTES;
-- Counter to define the transmission period between consecutive frames
signal SendPacketCountxDP, SendPacketCountxDN : unsigned(9 downto 0);
-- Ethernet PHY TX-related signals
signal TxEnxSP, TxEnxSN : std_logic; -- Transmit enable register
signal TxErrxSP, TxErrxSN : std_logic; -- Transmit error register
signal TxDataxD : std_logic_vector(7 downto 0); -- Data to be transmitted
-- Signals for the ethernet_crc block
signal CrcSofxSP, CrcSofxSN : std_logic; -- (active high) indicates start of new frame
signal CrcEofxSP, CrcEofxSN : std_logic; -- indicates End Of Frame (active high)
signal CrcDataValidxSP, CrcDataValidxSN : std_logic; -- indicates valid data at the CRC generator input
signal CrcByteInxD : std_logic_vector(7 downto 0); -- byte for the crc calculation
signal CrcValidxSP, CrcValidxSN : std_logic; -- (active high) indicates that crc result is valid
signal CrcValuexDP, CrcValuexDN : std_logic_vector(31 downto 0); -- current crc value from the crc generator
-- CRC value to transmit: Latest CRC value with bytes reversed (LSB becomes MSB) and all bits inversed
signal TxCrcValuexD : std_logic_vector(31 downto 0);
-- Signals for the FIFO
signal FifoRdEnxS : std_logic := '0'; -- FIFO Read Enable signal
signal FifoEmptyxS : std_logic; -- FIFO Empty signal
signal FifoDataOutxD : std_logic_vector(7 downto 0);
signal FifoRdCntUxD : unsigned(11 downto 0); -- FIFO Read data counter (unsigned)
-- Signals related with the construction of the various fields of the Ethernet Frame
signal EthernetHeaderxD : std_logic_vector(111 downto 0); -- the Ethernet header
signal EthernetPreamblexD : std_logic_vector(63 downto 0); -- the Ethernet preamble
signal IPHeaderxD : std_logic_vector(159 downto 0); -- the IP header
signal IPLengthxD : unsigned(15 downto 0); -- the IP Length in bytes
signal IPHeadCheckSumxD : unsigned(15 downto 0);
signal IPHeadExtCheckSumxD : unsigned(16 downto 0);
signal UDPHeaderxD : std_logic_vector(63 downto 0); -- the UDP header
signal UDPLengthxD : unsigned(15 downto 0); -- the UDP datagram length in bytes
signal UserDataLengthxDP, UserDataLengthxDN : unsigned(10 downto 0); -- Register that holds the user data length in bytes
signal TxCarrierExtSymbolsxS : std_logic := '0'; -- '1' if we need to transmit carrier extension symbols, '0' otherwise
begin -- behavioral
-----------------------------------------------------------------------------
-- Instances
-----------------------------------------------------------------------------
crcGenerator_1: crcGenerator
port map (
ClockxCI => Clock125xC,
ResetxRBI => ResetxRB,
NewFramexSI => CrcSofxSP,
DataInxDI => CrcByteInxD,
DataValidxSI => CrcDataValidxSP,
EndOfFramexSI => CrcEofxSP,
CrcxDO => CrcValuexDN,
CrcValidxSO => CrcValidxSN);
-----------------------------------------------------------------------------
-- Signal Assignments
-----------------------------------------------------------------------------
--SendPacketCountxDN <= SendPacketCountxDP + 1;
BusyxSO <= '1' when StatexDP /= RST and StatexDP /= IDLE else '0';
-- Clock and reset signals assignments
Clock125xC <= GmiiGTxClkxCI;
ResetxRB <= ResetxRBI;
-- Ethernet PHY signals
GmiiTxEnxSO <= TxEnxSP;
GmiiTxDataxDO <= TxDataxD;
GmiiTxErxSO <= TxErrxSP;
-- FIFO Signals
FifoRdEnxSO <= FifoRdEnxS;
FifoDataOutxD <= FifoDataOutxDI;
FifoEmptyxS <= FifoEmptyxSI;
FifoRdCntUxD <= unsigned(FifoRdCntxDI);
CrcByteInxD <= reverseByte(TxDataxD); -- crc input byte is the reversed transmitted byte in TxDataxD
TxCrcValuexD <= not crcReversedBytes(CrcValuexDP);
-- UDP Length: Length (in bytes) of the entire datagram: UDP header + UDP payload
UDPLengthxD <= UDPHeaderxD'length + resize(UserDataLengthxDP, UDPLengthxD'length);
-- IP Length: all data without the Ethernet header and without the Ethernet
-- CRC. Thus we need the length of the UDP packet and the length of the IP
-- header in bytes.
IPLengthxD <= UDPLengthxD + (IPHeaderxD'length/8);
-- If user data are less than minimum size then transmission of Carrier
-- Extension Symbols is needed. Set the flag.
TxCarrierExtSymbolsxS <= '1' when to_integer(UserDataLengthxDP) < MIN_UDP_BYTES else '0';
-- Headers. All transmitted MSByte first / LSBit first
EthernetPreamblexD <= ETH_PREAMBLE;
EthernetHeaderxD <= DEST_MAC_ADDRESS & SRC_MAC_ADDRESS & ETH_TYPE;
IPHeaderxD <= IP_VERSION & IP_HDR_LENGTH & IP_TOS & std_logic_vector(IPLengthxD) & IP_MSG_ID & IP_FLAGS & IP_TTL & IP_PROTOCOL & std_logic_vector(IPHeadCheckSumxD) & SRC_IP_ADDRESS & DEST_IP_ADDRESS;
UDPHeaderxD <= SRC_UDP_PORT & DEST_UDP_PORT & std_logic_vector(UDPLengthxD) & UDP_CHECKSUM;
-- purpose: Compute the IP Header Checksum
-- type : combinational
-- inputs : IPHeaderxD
-- outputs: IPHeadCheckSumxD
ipheader_checksum: process (IPHeaderxD)
begin -- process ipheader_checksum
IPHeadExtCheckSumxD <= (others => '0'); -- initialize
for i in 0 to IPHeaderxD'length/8-1 loop
if i /= 10 and i /= 11 then -- ignore the checksum bytes
IPHeadExtCheckSumxD <= IPHeadExtCheckSumxD + unsigned(IPHeaderxD((IPHeaderxD'length-1)-8*i downto (IPHeaderxD'length-8)-8*i));
end if;
if IPHeadExtCheckSumxD(IPHeadExtCheckSumxD'high) = '1' then
IPHeadExtCheckSumxD <= '0' & IPHeadExtCheckSumxD(IPHeadCheckSumxD'high downto 0) + to_unsigned(1, IPHeadExtCheckSumxD'length);
end if;
end loop; -- i
IPHeadCheckSumxD <= not IPHeadExtCheckSumxD((IPHeadcheckSumxD'length-1) downto 0);
end process ipheader_checksum;
-----------------------------------------------------------------------------
-- Processes
-----------------------------------------------------------------------------
-- State machine
fsm_memless : process (CrcDataValidxSP, EthernetHeaderxD, EthernetPreamblexD,
FifoDataOutxD, FifoRdCntUxD, IPHeaderxD,
InStateCountxDP, ResetxRB, SendPacketCountxDP,
StatexDP, TxCarrierExtSymbolsxS, TxCrcValuexD,
TxEnxSP, TxErrxSP, UDPHeaderxD, UserDataLengthxDP)
begin -- process fsm_memless
---------------------------------------------------------------------------
-- Defaults
---------------------------------------------------------------------------
StatexDN <= StatexDP;
TxEnxSN <= TxEnxSP;
TxErrxSN <= TxErrxSP;
TxDataxD <= (others => '0');
UserDataLengthxDN <= UserDataLengthxDP;
FifoRdEnxS <= '0';
CrcSofxSN <= '0';
CrcEofxSN <= '0';
CrcDataValidxSN <= CrcDataValidxSP;
SendPacketCountxDN <= SendPacketCountxDP + 1;
if InStateCountxDP < MAX_UDP_BYTES then
InStateCountxDN <= InStateCountxDP + 1;
else
InStateCountxDN <= 0;
end if;
---------------------------------------------------------------------------
-- States
---------------------------------------------------------------------------
case StatexDP is
-------------------------------------------------------------------------
-- Come and remain here as long as the block is in reset
-------------------------------------------------------------------------
when RST =>
if ResetxRB = '1' then
StatexDN <= IDLE;
end if;
-------------------------------------------------------------------------
-- Wait until time for next Ethernet frame transmission has come
-------------------------------------------------------------------------
when IDLE =>
if SendPacketCountxDP = 0 and FifoRdCntUxD /= 0 then -- and FifoRdCntUxD >= 1472
TxEnxSN <= '1';
InStateCountxDN <= 0; -- reset counter
StatexDN <= ETH_PRE; -- Go to transmit the Ethernet preamble
end if;
-------------------------------------------------------------------------
-- Transmit the Ethernet Preamble (8 byte / 64 bit)
-----------------------------------------------------------------------
when ETH_PRE =>
TxDataxD <= EthernetPreamblexD((EthernetPreamblexD'length-1)-InStateCountxDP*8 downto (EthernetPreamblexD'length-8)-InStateCountxDP*8);
if InStateCountxDP = 7 then -- End of ethernet preamble transmission
CrcSofxSN <= '1'; -- a new frame now starts for which CRC is to be computed
CrcDataValidxSN <= '1'; -- From now on Tx data are valid for CRC
InStateCountxDN <= 0; -- reset counter
StatexDN <= ETH_HEADER; -- Go to transmit the Ethernet header
end if;
-------------------------------------------------------------------------
-- Transmit the Ethernet Header (14 byte / 112 bit)
-------------------------------------------------------------------------
when ETH_HEADER =>
TxDataxD <= EthernetHeaderxD((EthernetHeaderxD'length-1)-InStateCountxDP*8 downto (EthernetHeaderxD'length-8)-InStateCountxDP*8);
if InStateCountxDP = 13 then -- End of Ethernet header transmission
if FifoRdCntUxD > MAX_UDP_BYTES then
UserDataLengthxDN <= to_unsigned(MAX_UDP_BYTES, UserDataLengthxDN'length);
else
UserDataLengthxDN <= resize(FifoRdCntUxD, UserDataLengthxDN'length);
end if;
InStateCountxDN <= 0; -- reset counter
StatexDN <= IP_HEADER; -- go to transmit the IP Header
end if;
-------------------------------------------------------------------------
-- Transmit the IP Header (20 byte / 160 bit)
-------------------------------------------------------------------------
when IP_HEADER =>
TxDataxD <= IPHeaderxD((IPHeaderxD'length-1)-InStateCountxDP*8 downto (IPHeaderxD'length-8)-InStateCountxDP*8);
if InStateCountxDP = 19 then -- End of IP header transmission
InStateCountxDN <= 0; -- reset counter
StatexDN <= UDP_HEADER; -- Go to transmit the UDP Header
end if;
-------------------------------------------------------------------------
-- Transmit the UDP Header (8 byte / 64 bit)
-------------------------------------------------------------------------
when UDP_HEADER =>
TxDataxD <= UDPHeaderxD((UDPHeaderxD'length-1)-InStateCountxDP*8 downto (UDPHeaderxD'length-8)-InStateCountxDP*8);
if InStateCountxDP = 7 then -- End of UDP header transmission
FifoRdEnxS <= '1';
InStateCountxDN <= 0; -- reset counter
StatexDN <= DATA; -- Go to transmit the user data
end if;
-------------------------------------------------------------------------
-- Transmit the User Data
-------------------------------------------------------------------------
when DATA =>
TxDataxD <= FifoDataOutxD;
-- Assert the End Of Frame signal
if InStateCountxDP = to_integer(UserDataLengthxDP) - 2 then
CrcEofxSN <= '1';
end if;
if InStateCountxDP = to_integer(UserDataLengthxDP) - 1 then
CrcDataValidxSN <= '0'; -- Data are not valid any more for CRC
InStateCountxDN <= 0; -- reset counter
StatexDN <= CRC; -- Go to transmit the calculated CRC
else
FifoRdEnxS <= '1';
end if;
-------------------------------------------------------------------------
-- Transmit the 32-bit CRC data
-------------------------------------------------------------------------
when CRC =>
case InStateCountxDP is
when 0 =>
TxDataxD <= TxCrcValuexD((TxCrcValuexD'length-1) downto (TxCrcValuexD'length-8));
when 1 =>
TxDataxD <= TxCrcValuexD((TxCrcValuexD'length-9) downto (TxCrcValuexD'length-16));
when 2 =>
TxDataxD <= TxCrcValuexD((TxCrcValuexD'length-17) downto (TxCrcValuexD'length-24));
when 3 =>
TxDataxD <= TxCrcValuexD((TxCrcValuexD'length-25) downto (TxCrcValuexD'length-32));
TxEnxSN <= '0'; -- de-assert the TX Enable signal
InStateCountxDN <= 0; -- reset counter
-- If the TxCarrierExtSymbolsxS flag is asserted, go to transmit
-- the carrier extension symbols. Otherwise the frame transmission
-- is over. Go to IDLE.
if TxCarrierExtSymbolsxS = '1' then
TxErrxSN <= '1'; -- Assert the TX_ER on next cycle
StatexDN <= ETH_EXT;
else
SendPacketCountxDN <= (others => '0');
StatexDN <= IDLE;
end if;
when others => null;
end case; -- InStateCountxDP
-------------------------------------------------------------------------
-- Transmit Carrier Extnesion Symbols until min frame length is reached
-------------------------------------------------------------------------
when ETH_EXT =>
-- Keep the TX_ER flag asserted until the min frame length is reached
if InStateCountxDP >= (MIN_UDP_BYTES - to_integer(UserDataLengthxDP) - 1) then
TxErrxSN <= '0';
InStateCountxDN <= 0; -- reset counter
SendPacketCountxDN <= (others => '0');
StatexDN <= IDLE; -- Frame transmission is over
end if;
end case; -- StatexDP
end process fsm_memless;
-- Registers
registers_memzing : process (Clock125xC, ResetxRB)
begin -- process registers_memzing
if ResetxRB = '0' then -- asynchronous reset (active low)
StatexDP <= RST;
TxEnxSP <= '0';
TxErrxSP <= '0';
UserDataLengthxDP <= (others => '0');
InStateCountxDP <= 0;
SendPacketCountxDP <= (others => '0');
CrcSofxSP <= '0';
CrcEofxSP <= '0';
CrcDataValidxSP <= '0';
CrcValuexDP <= (others => '0');
CrcValidxSP <= '0';
elsif Clock125xC'event and Clock125xC = '1' then -- rising clock edge
StatexDP <= StatexDN;
TxEnxSP <= TxEnxSN;
TxErrxSP <= TxErrxSN;
UserDataLengthxDP <= UserDataLengthxDN;
InStateCountxDP <= InStateCountxDN;
SendPacketCountxDP <= SendPacketCountxDN;
CrcSofxSP <= CrcSofxSN;
CrcEofxSP <= CrcEofxSN;
CrcDataValidxSP <= CrcDataValidxSN;
CrcValuexDP <= CrcValuexDN;
CrcValidxSP <= CrcValidxSN;
end if;
end process registers_memzing;
end behavioral;
The GMII interface has the GmiiGTxClkxCI, GmiiTxEnxSO, GmiiTxErxSO and GmiiTxDataxDO signals. And so GmiiGTxClkxCI is the clock reference of the other three. So what I am thinking is that since the block is clocked by the Clk125MxC signal whereas the clock that the 88E1111 PHY chip receives is the GmiiGTxClkxCO from the ODDR2, is there any problem in that? I mean most probably what I'm saying is stupid, but I'm really confused.
Anyway, thank you for the help!
Nikos
robn
lace:1137 - This design is not guaranteed to be routable! This design
