If you reference a specific error message code, you should include the text of the error message in your post. I am not familiar with "DCM clocking error 1203".
If the question is:
How do I forward an internal global clock to an output pin?
the answer is an approach which is
- well documented
- applies (generally) to all FPGA families
- called 'clock forwarding'
Specifically, try the following:
- Open ISE
- Click on the 'light bulb' icon to bring up the Language Templates window
- Follow Verilog (or VHDL)>Synthesis Constructs>Coding Examples>Misc>Output Clock Forwarding Using DDR
- Read the Info section, as well as the family-specific sections
For Verilog and Spartan-6, you will find the following example:
// Clock forwarding circuit using the double data-rate register
// Spartan-3E/3A/6
// Xilinx HDL Language Template, version 13.4
ODDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) clock_forward_inst (
.Q(<output_clock>), // 1-bit DDR output data
.C0(<internal_clock>), // 1-bit clock input
.C1(~<internal_clock>), // 1-bit clock input
.CE(<stop_clock>), // 1-bit clock enable input
.D0(1'b0), // 1-bit data input (associated with C0)
.D1(1'b1), // 1-bit data input (associated with C1)
.R(<hold_clock_low>), // 1-bit reset input
.S(<hold_clock_high>) // 1-bit set input
);
// End of clock_forward_inst instantiation
The following example showing clock forwarding to an output pin is edited from UG382, Figure 3-13:
-- Bob Elkind
