10-24-2009 02:08 PM
I tried to covert some non-standard video signals into vga signals with Spartan3e.
I want to recover a pixel clock (about 17.25MHz) from the horizontal synchronization signal whose frequency is 24 KHz . I used DFS of DCM and input 24khz hs to get the clock (17.25M) in VHDL, and it is ok in behavior simulation with ISE11. However, the minimum requirement of input of DCM’DFS is 200khz, I cannot implement it with Spartan3e.
Since I don’t want to use external PLL, I tried to use another high frequency clock (around 50M), counters (for phase shift) and XOR gates to multiply the 24khz up to 384khz (24x16), which is over the minimum requirement. But the DCM seems it cannot catch the 384khz signal as clock signal, in the simulation there are a few pulse coming out and then stop with nothing, even though I raised the high frequency clock’s frequency to over 200M for more accuracy. I know the 384khz signal I made from counters and gates is not good enough as clock signal, but how can get it without pll?
Can anyone give me advice to make frequency multiplier without external pll? Or any way to go through the minimum frequency requirement of DCM by using Spartan3e’s internal resource.