Spartan® Family FPGAs

[giacciocl]

Hi All,

I need your help for the item into subjet.

I have to build an interface for an application where the operative frequency starts from 400 KHz (during the inizialization phase), and can reach 200 MHz. Moreover for the frequency up to 52MHz, the application can work in DDR mode.

At the moment I have a design based on ODDR2 and IDDR2, and it seems working properly, but I'm not able to implement the 200 MHz SDR.

For this feature I'm thinking to use the ISERDES and OSERDES. Take into account the either when the data are sent either when the data are received, the clock is sent from my application towards the target.

Could you suggest me which architectural scheme I have to implement for managing this wide frequency range?

I can reach with no particular problem the 50 MHz as internal frequency. So I can save a 4:1 serialization factor (the same for the de-serialization).

I'm thinking to generate the frequency by a PLL, but it is not completely clear in which way I have to complete the scheme. For example, Do I need an IODELAY block on the clock which sent towards the target? Or I have to use this block only on the data pattern? Is this new architecture able to save what is already workable? etc etc.

Please could someone help me?

Thanks a lot

Claudio

[giacciocl]

Hi Guys,

please, is there someone which could help me?

Thank you so much

Claudio

[rcingham]

Is the 400kHz-to-200MHz the only clock to the FPGA?
If so, I cannot imagine any way that it can detect which side of 52MHz it is, nor generate a stable 200MHz clock.

With a separate 200MHz clock source, you can do these things, but how would require a lot more detail on the application interface.

[giacciocl]

The system clock is 50 MHz. This clock goes into PLL ADV in order to generate different frequency up to 200MHz.

The 400KHz clock, instead is generated by an internal divided starting from the system clock.