Spartan® Family FPGAs

[pumaju1808]

hi,

i want to konw if it is possible make partial reconfiguration using Spartan 6 devices, it is possible using its ICAP modules??

and also i want to know what tools are available to do this??

regards

[austin]

p,

http://www.xilinx.com/support/documentation/user_guides/ug380.pdf

Go to the chapter on "ICAP"

There is no support for PR at preset (you are on your own, using whatever hasa already been published).

There will be support in ISE 12, fully rethought, and properly done (for the fourth time).

Partial Reconfiguration hasa for a long time been considered like an extreme sport:  fun to watch, difficult to do well.  More than once we have attempted to provide a means to make it workable, and supportable.  In version 12 of the tools, we believe we may have finally figured it out.  Time will tell.

[mnjourdan]

Are you saying that there will be support for PR in the Spartan6 in 12.1?  I thought the design of the IO banks was done differently than the V6 and PR was not possible. 

[austin]

m,

Yes, there are dynamic reconfiguration ports (DRP) in the top and bottom banks of IOs in S6, and that would make it harder for reconfiguration, as these two features "collide."  I am just guessing, but if you did not use the DRP for the top and bottom IO banks, and you also were careful about (not) using SRL's, there is nothing missing in the hardware that would prevent partial reconfiguration ...

As to if S6 PR flow will be in ISE 12, I would guess that V6 has priority (and the customers), so wide-spread S6 support for PR is unlikely.

I was primarily addressing those students who want to do PR on Virtex 4 and Virtex 5.

[davidd]

The Partial Reconfiguration software flow introduced in 11.1 and released as a product in 12.1 does not and will not support Spartan-6.  This solution supports Virtex-4, Virtex-5 and Virtex-6, and the first Spartan-class support will be with our next generation of silicon.  Spartan-6 PR is still supported via the difference-based approach documented in XAPP 290.

thanks,

david.

[ickebrennbart]

Hello,

I am still very unexperienced in the whole topic of (partial) dynamic reconfiguration, but want to get into more details with my master thesis. For that I would like to make use of that feature. First I need to find out which FPGA I can use. In general that cheaper FPGA that better for me.

Even after reading this and some other threads it is not completely clear to me whether I can use a S6 for my application or not. That is why I would like to describe my application.

I want to use any FPGA to implement a Microblaze running a genetic algorithm. In parallel to the microblaze will be some logic performing a task. The GA on the microblaze is supposed to change the logic (reconfigure it) when necessary. Therefore the MB should continue to run while changing the logic and their connections.

Is that possible with a S6? (ISE 11.5)

Thanks a lot

Jens

[pumaju1808]

Hi,

Can i follow the PR workshop materials with spartan-6 FPGA (SP605)??, this workshop materials are for Virtex-5, but i want to follow using SP605, of course, doing the appropiate changes, but i want to know if it is possible.

And also if PR for Spartan-6 use the same design flow than Virtex FPGAs??

i appreciate your help, thanks

[davidd]

To reiterate my post from last May:

Spartan-6 Partial Reconfiguration will only ever be supported by the difference-based flow as described in XAPP290:  http://www.xilinx.com/support/documentation/application_notes/xapp290.pdf. 

It will never be supported by the Partition-based approach described in UG702:  http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ug702.pdf or any of the related tutorials (i.e. UG743) found here:  http://www.xilinx.com/tools/partial-reconfiguration

Artix-7, Kintex-7, Virtex-7, and Zynq-7000 will all be supported by both flows in due time.  Look for K7 and V7 in the next update of ISE software.

thanks,

david.

[dropsy]

hi Jens,

My name is Dave, I am EE masters student. I am starting my thesis this summer in the area of dynmic reconfiguration. Microbraze or PowerPC is to be the main intelligent control manager for the reconfiguration process. Its kind of similar to your project where you implemented a genetic algorithm on MircoBlaze. Please tell me how you went about implementing your design on the Virtex 6 (if you eventually used it).

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ickebrennbart wrote:

Hello,

I am still very unexperienced in the whole topic of (partial) dynamic reconfiguration, but want to get into more details with my master thesis. For that I would like to make use of that feature. First I need to find out which FPGA I can use. In general that cheaper FPGA that better for me.

Even after reading this and some other threads it is not completely clear to me whether I can use a S6 for my application or not. That is why I would like to describe my application.

I want to use any FPGA to implement a Microblaze running a genetic algorithm. In parallel to the microblaze will be some logic performing a task. The GA on the microblaze is supposed to change the logic (reconfigure it) when necessary. Therefore the MB should continue to run while changing the logic and their connections.

Is that possible with a S6? (ISE 11.5)

Thanks a lot

Jens

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PS: anyone else, please feel free to reply.

dave