Spartan® Family FPGAs

[omidsht]

Hi
I have made a pcb board of the attached schematic, but I it has a problem. When I
program the FPGA (xc3s400) solely through jtag (Platform cable usb II) the FPGA is program and okay, also when I
program the FLASH (xcf04s) solely it is programmed as well (as impact says), but the problem is this that after programming the FLAHS,
the FPGA is not configured and programmed by FLASH through master serial mode! as I check the DONE pin of FPGA, it never comes high ( it is low, indicating that FPGA has not
been configured by FLASH), also the CCLK pin of FPGA continues to pulsing the CLK pin of FLASH for ever!
I checked every thing but I couldnt find out what is the problem . I would be very thankfull if somebody can help me solving this problem
thanks in advance
Regards

[kuldipsingh1]

Looks like M0 mode pin need to be at Logic 1(High) for Master SPI mode. Please check.

Thanks

KDS

[gszakacs]

---

kuldipsingh1 wrote:

Looks like M0 mode pin need to be at Logic 1(High) for Master SPI mode. Please check.

Thanks

KDS

---

Actually, the XCF04S is not a SPI device, so the Master Serial mode (M[2:0] = "000") is correct.

There are many things that can result in DONE not going high, but the fact that JTAG seems to work correctly

is a good sign and probably means that the power supplies are OK.  Some things to check:

Make sure the .mcs file was properly prepared for the XCF04S.  Impact should correctly order the

bits within bytes, but only if it uses the correct device when preparing the PROM image.  I don't

think the bit shift order is the same for SPI and Platform Flash parts.

Any problem that could result in CRC errors will cause the INIT_B line to assert low after config

has begun.  Check the activity on this line to see if this happens (refer to ug332).

Poor signal integrity on the CCLK line can cause data errors.  Since the FPGA is driving the signal,

you should check its integrity at the XCF04S to see if there is any severe overshoot, undershoot,

or ringing that could cause unwanted clocking of the XCF04S.

You might want to search through these forums for other configuration issues that might

resemble your problems.  "DONE did not go high" is a good search term.

-- Gabor

[eteam00]

I concur with everything Gabor wrote.

The XC3S400 TDI pin should have a series current-limiting resistor, same as TMS and TCK inputs, because the TDO output from the platform flash is 3.3V logic HIGH.  This won't solve your config problem, but keep this in mind if/when you update the circuit board layout.

Also, it would be wise and prudent -- if/when you update the circuit board layout -- to insert a 33-ohm series termination resistor at the FPGA's CCLK output.  This will eliminate any signal integrity concerns with this signal.

The CONFIGRATE setting in ISE (or PROMGEN) should be no higher than 22MHz.  Including the +/- 50% tolerance from the CONFIGRATE setting, this will meet the 33MHz max CCLK frequency of the XCF04S.

UG332, v1.6 has a step-by-step process for generating bitstream and PROM file for the Platform Flash devices, starting on page 91.

-- Bob Elkind

[omidsht]

I checked the signal integrity of CCLk on Osc.Scope , not bad. also I check the clk of speed of configration not to be more than 22 mhz.

I checked the init_B pin on scope and i saw that it toggles (comes low then high) for 2 or 3 timeswhen i program the flash. also the follwoing messahe appears on impact after programming flash with option LOAD FPGA :  "INFO:iMPACT:563 - '1':Please ensure proper connections as specified by the data book ..." !!!!

the full message is here:

"

// *** BATCH CMD : Program -p 1 -e -loadfpga
Maximum TCK operating frequency for this device chain: 15000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Erasing device...
PROGRESS_START - Starting Operation.
'1': Erasure completed successfully.
'1': Programming device...
done.
'1': Putting device in ISP mode...done.
'1': Putting device in ISP mode...done.
'1': Setting user-programmable bits...
done.
'1': Putting device in ISP mode...done.
'1': Starting FPGA Load with Prom Data...INFO:iMPACT:563 - '1':Please ensure proper connections as specified by the data book ...
'1': Programming completed successfully.
'1': Programming completed successfully.
PROGRESS_END - End Operation.
Elapsed time =     12 sec.

"

I attach the pcb file here as well.

[gszakacs]

You say that INIT_B toggles several times while programming the flash?  Can you verify the

flash contents after programming.  I think that normally Impact will verify after programming

unless you un-check this option.  However I don't see any message like "Verifying..." in your

Impact output.

I know that there are issues with chaining XCF04S and Spartan 3 parts that can affect

JTAG programming.  I originally thought that this was a startup issue rather than

programming, however unless you can prove that the flash was in fact programmed

reliably, I think you may be looking at a JTAG programming issue.

I tried to look at the file you attached, but I don't know what a .pcbdoc file is.  Is this

the board layout?

-- Gabor

[aeke]

Check the bit file generation options. Some times the tool can be configured to select JTAG clock for the innitialization process instead of CCLK. Then the configuration from FLASH goes ok but the innitialization (DONE signal process) does not work because the FPGA is missing the necessary additional clocks.

[omidsht]

- The second attached file is the layout (Altium DXP software).

- About verifying flash; Yes, I can verify the flash and verification is done succefully (it is not mentioned in the above message of impact because i unchecked its option myself).

- About bit file generation options; it is set to CCLK.

a question : is it possible that the version of ISE that I use has buggs with this Architecture ? (I use ISE 10.1)?