Spartan® Family FPGAs

[chongyang1999]

Hi all:

     I'm a new user of spartan 6 GTP,I use two custom designed boards to implement a clock transfer through optical fiber, and now at the receiver end the recovered clock is sychronized with the transmitter one.

    The problem is the phase difference between these two clocks is not fixed after every power cycle, according to some article, one of the reason is because the Parallel Clock Divider doesn't care the phase of the recover clock, we can only solve the problem by using rx_slide signal in PMA mode to adjust the phase of the recovered clock. Is this true ?

    In order to use the rx_slide signal, it seems we need to design a custom comma detection and alignment module to replace the orignal one, according to page 101 of UG386, it is possible to bypass the comma detection module but keep the 10b/8b decoder, can any one tell me how can I achieve this ? except port  RXDATA is there any other port can be used to access the 10bit receive data? 

    Thanks very much for your kindly help in advance.

[mcgett]

If you are using 8B10B as part of your protocol then you must also use comma alignment in order for the receiver to align with serial datastream to 10-bit boundaries (the transmitter must send the same alignment commas that the receiver is expecting) in order for this to be decoded back to 8-bits.  There is no need to use RXSLIDE to do this. 

[chongyang1999]

Thank you for your kindly reply.

Maybe I'm not clear enough, what we want  is the recovered clock has a fixed phase difference with the reference clock  at the transmit end after each power cycle . In order to achieve this, we have to adjust the phase of recovered clock by RXSLIDE, so maybe we need a custom designed comma detection and alignment module. But at the same time, we want to keep the orignal 10b/8b module. Is this possible ? If so, how can I do ? If not, could you please tell me how can I achieve the fixed phase difference ?

Best regards!

[mcgett]

> what we want  is the recovered clock has a fixed phase difference with the reference clock  

You have two boards with two different reference clocks which means that the reference clock on each board will be different in frequency and phase.  Why does the recovered clock matter in your system?  Since you are also using 8B10B the next logical step is to use clock correction and the reference clock for both TX and RX data paths ignoring the recovered clock completely.

Design two distinct system to operate in lock step with each other is a very difficult task. 

[chongyang1999]

Hi :

    Our system is similar to SDH ,first, the two boards will work at independent clock, after connection is established, one board will use the recovered clock as a reference clock. In this way, the two boards can work at the  same clock frenquency with different phase. It's actually a clock distribution system .And not only the frenquency but also the phase are very important to our application, so I need a fixed phase difference.