Spartan® Family FPGAs

[devik]

Hi,

i'd like to ask how can one debug JTAG stream loading. I've xc3s50a connected on pcb to

ARM cpu via JTAG pins.

I generated test logic .bin by bitgen (10.1.03 linux version) and loaded via own TAP

loader (sequence  CFG_IN, DR<=stream, JSTART, DR<=40 extra TCKs).

Option StartUpClk:JtagClk set.

When I read STAT register it is 1BC4 (DCM up, INIT up, no err) after power up.

After the first bitstream load and JSTART it is 1BE4 - thus GHIGH-B was deasserted

(probably  caused by LFRM command in the stream) but none of DONE, GWE, GTS

and error flags are active.

It is weird state - as if startup sequence state machine was not started.

Now when I reload the image (CFG_IN/JSTART) using the same routine, flags

goes to  3BFC (DONE, GWE, GTS up) and device actualy works.

After sending JPROGRAM, I have again use two programing rounds.

Any clue how one could debug this ? Can I somehow read state of startup FSM ?

LOUT seems interesting but not supported in JTAG ...

thanks a much, Martin

[mkajdas]

I use ISE 10.1.03 on Win XP with USB JTAG cable and I always need to program my XC3S50AN twice.

iMPACT can read the ID correctly but the first program cycle always failes right away, second time it works.

I also would like to know the reason why.

M.

[devik]

Just some new informations I gathered. I found new anomalies whose could have the same roots.

The pin P53 which is dual purpose CCLK in xc3s50a-vq100 is not usable as output. A created

almost empty verilog and used bitgen -g UnusedPin:PullUp - all pins (I measured about 40) are

up except P53. P53 is probably input pulled down (CCLK??).

BUT - when I reset the part (and I use PUDC_B pin to force pullups) the P53 is pulled up.

Summary: P53 is not damaged, some logic is holding it as input.

Hypothesis:  configuration process doesn't end correctly even if DONE is finally up,

     and it uses CCLK as clock input forever (despite setting jtag startup clock)

I did test to verify it. I created bitstream with startup clock set to CCLK and loaded it via

JTAG. Well it started up in the same way (on second load) !!  I checked resulting

bitstream and COR1 COR2 and CTL are loaded as expected.

I also tested WebPack 11 in hope something get fixed - the same results (need to config

twice, P53 not working).

Just note, I already loaded a few designs, using 60% of pins, BRAM, DCM, JTAG USER1/2

and all works well.

Only I don't want to release design to volume manufacturer until I resolve this mess.

[devik · Accepted solution]

Well, I solved it. I compared my sequence with generated SVF and found that I was

loading JSTART and the going directly do DR state, then to IDLE.

Going into IDLE and clocking it solved both problems - double loading and P53 pin.

Just for information, setting startup clock to UserClk  and connecting clock to that

user pin works too. When clock on that pin is unconnected, you can STILL start

the design by loading it twice but startup FSM can't finish correctly and CCLK pin

will be unusable.

It is interesting that it can be started without valid CCLK ...

I hope this can help someone with debugging similar problems. At least for me

it have got me deeper insight into configuration part of process.