Spartan® Family FPGAs

[alireza_1361]

hi 

I am working on a board with xc6slx75 and xcf32p in selectMAP setup . i can program both fpga and platform flash with jtag interface BUT xcf32 dosn't load in fpga after power up or prog_b asserted or actived (low)  .

i much sure that schematic is correct , i use figure 2-6 in (page 30) of UG380.pdf .

cclk run 10 cycle after prog_b then it will be down .

i dont know ! Please Help me to solve my problem

tnx .

[eteam00]

You should post your board schematic.

You should check the behaviour of the INIT_B pin.  If INIT_B pin goes LOW, this indicates a CRC error.

What BitGen settings are you using?

-- Bob Elkind

[gszakacs]

A common mistake in many newbie designs is to use large values for pull-down

resistors on the mode inputs M1 and M2.  These can be insufficient to pull down

against the internal pull-up on the mode pins.  If you don't tie the mode pin directly

to ground, you should use a value less than 1K Ohm (check the device data sheet

for pullup current for your device - the value may need to be even smaller).

If you hook Impact up to the board with a standard JTAG cable, then after powering the

board on, you should be able to use the Debug menu of Impact to read the current

status of the configuration logic.  This often gives clues as to what is going on.  This

is also a good way to see the current state of all configuration pins without probing

around the board.

-- Gabor

[alireza_1361]

thanks for the answer.

 my schematic completely similar to ug380 selectMAP with two  difference :

first :  in  HSWAPEN PIN that is float .(i connect it to ground but dont solve !)

second : in CCLK termination . i don't mount the parallel resistor to Vcco and ground .

init_B  go low with prog_b active low and go back high with prog_b   .

prog_b----------------____________------------------------------

init_b -----------------____________------------------------------

cclk-----------------------------------------|||||||||||||||||_________(100 cycle fix) (500 ns high(amp 1.5 v) 500 ns Low (0 v)) 

is high amplitude of cclk sufficient ?

d[0 to 7]-----------------------------------|||||||||||||||||_________all data pin have chenge differently. 

i don't use or change BitGen Setting . i Generate .MCS File from .Bit file  (with Default setting) thet work properly .

and mode pin :M[1]& M[0] connected to Ground with 0 ohm resistor . 

in device programing properties in IMPACT i check that :

* load FPGA 

* Parallel MODE

* During Configuration :PROM is Slave(Clocked externally )

and finally  Read Device Status create this report :

INFO:iMPACT - Current time: 6/10/2012 8:47:47 AM
Maximum TCK operating frequency for this device chain: 15000000.
Validating chain...
Boundary-scan chain validated successfully.
'2': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[2] RESERVED : 0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR : 0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR : 0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[8] RESERVED : 0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR : 0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR : 0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
'2': Reading status register contents...
[0] CRC ERROR : 0
[1] IDCODE ERROR : 0
[2] DCM LOCK STATUS : 1
[3] GTS_CFG_B STATUS : 0
[4] GWE STATUS : 0
[5] GHIGH STATUS : 0
[6] DECRYPTION ERROR : 0
[7] DECRYPTOR ENABLE : 0
[8] HSWAPEN PIN : 1
[9] MODE PIN M[0] : 0
[10] MODE PIN M[1] : 0
[11] RESERVED : 0
[12] INIT_B PIN : 1
[13] DONE PIN : 0
[14] SUSPEND STATUS : 0
[15] FALLBACK STATUS : 0

[alireza_1361]

before this i use pullup for cclk ! and when i remove it resulte was change as follow :

excuse me !!!!!

i modify wave form :

            _____________________________             ____________________________________

prog_b :                                                   |_______|

                                                                            _______

init_b:______________________________________|   |    |    |_____________________________ 

cclk________________________________________||||||||||||||||||_____________________________

cclk 214ms clocked with 500n/500n dutysycle and 1.2 v high and 0v low  

                                                                             ______

all data pin __________________________________|           |_____________________________

[alireza_1361]

i mount termination resistor on cclk and cclk completely damaged and its amplitude reduced to 150mv or less !

----------------||-----------------~~~~~---------------|------------------~~~~~--------------------||------------------

 vcco        100n           100 ohm          cclk              100 ohm                100n            gnd

[alireza_1361 · Accepted solution]

it worked . i forget mount ferrite bead of Vcco in FPGA .

tnx

[matrix39]

Can you please specify the the voltage level of the VCCO and the part no of the Bead used OR atleast the frequency range, impedance and DC resistance. i have not seen such a  bead on FPGA banks in any of the FPGA design yet.

thanks with regards

Matrix

[eteam00]

matrix,

If you want to discuss ferrite beads for power supply filtering, then please start a new thread.  This thread is marked 'solved', and has nothing to do with ferrite beads.

Thank you for your consideration.

-- Bob Elkind