spartan6 gtp pll lock problem

ckiziloz · ‎05-26-2012

I will output a hd sdi video on my board. There will be only hd sdi output, not an input on project. I used Spartan gtp wizard and triple sdi core. Everything is OK on simulation, but it didn't worked on hardware. The gtp dual tile pll didn't work fine. PLLLKDET0 net didn't go high, although it goes on simulation. On board design, I wired all the mgt power pins(but not MGTAVCCRX pin ) to 1.2 volt. As I don't need input hd sdi, I wired the MGTAVCCRX pin to ground. Is this a bad practice? Can it affect my ref clk input? Do I have to change my design?

mcgett · ‎01-03-2008

All of the MGT supply pins must be powered to the data sheet voltage levels. You need to fix this on your board.

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ckiziloz · ‎05-26-2012

Thank you, I will fix it on the board.

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Spartan® Family FPGAs

spartan6 gtp pll lock problem

Re: spartan6 gtp pll lock problem

Re: spartan6 gtp pll lock problem