Synthesis

[zohair01]

I have BRAMs in my design. During simulation I used coe files to generate mif files to act as initialization for the RAMs. But is this possible during synthesis? Am I able to transmit memory information along with the bit file?

[rcingham]

Which FPGA?
What version of tools?
Are you inferring the BRAM, or did you use the 'Block Memory Generator'?

[eilert]

Hi,

basically yes.

Even after Place & Route you can change the BRAM initial values in the bitfile with the data2mem tool without needing to rerun the whole implementation.

Read the data2mem documentation for details.

Have a nice synthesis

   Eilert

[barryabrown · Accepted solution]

You initialize the block ram in coregen with your coe file - the resulting ngc includes the initial values.  Since you have created a coe and generated a mif, you have probably done this already.

Barry

[zohair01]

I see. I was under the impression that since the mif file was generated, that it is only for simulation. OK. That makes sense. Thanks.