02-15-2009 02:51 PM
Guys, sometimes I feel I have to give up... Is so hard to work with ISE. Recently I just have written a simple barrel shifter. Code:
entity bshifter is
Port ( CLR : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR (2 downto 0);
O : out STD_LOGIC_VECTOR (2 downto 0);
C : in STD_LOGIC);
architecture Behavioral of bshifter is
signal BSH : std_logic_vector(2 downto 0);
process (C, CLR, DIN)
if CLR = '1' then
BSH <= DIN;
elsif rising_edge(C) then
BSH(1) <= BSH(0);
BSH(2) <= BSH(1);
BSH(0) <= BSH(2);
O <= BSH;
The result is this:
Of course it does not work.
I just have put the same code into Quartus (Altera) and got this result:
And of course this works perfectly. I simply don't understand how this horrible bug can be found in a such software??? ISE in general has many-many bugs, this is why I started to deal with Altera chips, perhaps their dev stuffs works well. I think this is a serious shame for the ISE developers.
02-15-2009 03:23 PM
now thats not good!
i had a look with ISE 8.1 (version after "the change") it gave somthing like your schematic.
i tried ISE 6.3 and got a DIFFERENT result.
i would post the images, but this forum want a URL to insert the image (save xilinx server space i guess) the truth is i cant be bothered to post the image elsewhere and link to it from here!
I'd like to thank you for posting this I wasnt aware of it :smileysad:
02-15-2009 04:14 PM
This is a nightmare. I tried to create a schematic, this one:
But because ISE has a serious bug not detecting any SCH change, I had to make a new empty project, copy all VHDL, SCH and UCF files, then I could apply the sch. Mapped the sch into VHDL, then checked the output. This is the result:
Have a see how O0-O2 behave at CLR assertion... and later. The clock is C. There is simply no any relation to the circuit, though in the RTL it showed correctly. I'm gonna retire now, I'm too old for such kind of idiotism.Every day I check for software update, but nothing happened, is possible that Xilinx is going to bankrupt, they run out of resources (developers I mean)??? Now this is what I have to think (world wide economy crash, etc.)
02-15-2009 04:31 PM
02-16-2009 06:50 AM
Why don't you say that what you attached is the technology schematic?
The RTL Schematic which the other people are talking about is wrong. Period.
This is an old problem of the RTL schematic viewer / generator.
It was always a problem with the RTL Sch not showing nets orother elements but xst does a good job and the final result works fine.
I would expect that Xilinx will drop this feature as they do with the waveform editor.
It's easier to drop features than fixing stupid bugs.
02-16-2009 09:02 AM
First of all I'm just a regular tool user like you.
The OP mentioned "it doesn't work", so I had thought he meant that it doesn't work on hardware. That's why I checked the technology schematic.
The RTL schematic has some problem, but if you can take a look at it a little bit closer, it is not entirely wrong. Actually other than the extra FDCP symblol at the top, it actually matches the RTL. I think the problem here is the RTL schematic abstracts the three registers into one FDCP symbol at the bottom, which is actually a register array.
I'm not defending the tool in any way. I'm just trying to help here so we can all get most out of the tool and get things done.
02-16-2009 09:28 AM
The fact is, Jim, as you can see the picture of scope, that this simple design won't work, even there is no any sense of the result. I don't say, that any setting change of the synthesis module could not help... I just simply have no clue what should I change.
The real trouble is that this bug is not the only one using ISE. Many small problems I had to face to, and try to find always some workaround. This is very tyring, and ineffective.
For some problems I have simply no answer. For example:
After some work with ISE it just changes its mind, and do not senses anymore that SCH file is changed. I had to be tricky changing the library files written in VHDL to force ISE to catch. Because it was a very energy wasting approach I just simply fed up suing scematic and designed everything in VHDL. Though is stil a problem, that the main file should be schematic for the better understandiung the people coming after me, you don't mind? Related to this problem cleaning project does not help at all, and if I "Update al schematic files", all sch files gets garbaged, unusable. I almost got heart attack once when this happened.
To be honest, I'm sad to say and I don't want to hurt anyone, but ISE (ver. 10.3) is the worst software ever I used in my life. And I'm not young, you know.It caused me very serious losses.
02-16-2009 09:40 AM
Well, if the design doesn't work when implemented then you must be doing something wrong.
I am using ISE for several years and I didn't had this type of problem.
It is arguable that the main file should be a schematic. I personally strongly disagree but I don't want to discuss too much about this.
If you are a beginner, then I have some bad news for you: I don't know any FPGA tool that will not make you pull your hair at some point.