I've written some code and been messing with it for quite a while now. I can get it to simulate fine with the Behavioral model but when I use the Post Translate model it won't simulate. I'm a bit of a novice but not sure where to look or exactly what this is telling me.
Any suggestions?
Thanks!
------- Here's the code I wrote. It won't drive the output when I simulate the Post-Translation model.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clkDiv is
-- Configure desired clock
generic(
baseClock : integer := 50000000; -- Frequency of input clock
outFreq : integer := 2500000 -- Desired output clock frequency
);
port (
reset : in STD_LOGIC; -- Resets clock / resyncs
clk_in : in STD_LOGIC; -- Base clock input
clk_out : out STD_LOGIC -- Generated clock output
);
end clkDiv;
architecture Behavioral of clkDiv is
-- Number of base clock pulses per output clock pulse
constant ticksPerOutClk : integer := 10;--baseClock / outFreq;
signal clkGen : std_logic := '0';
begin
clk_out <= clkGen;
process( reset, clk_in ) is
variable cycle_counter : integer range 0 to ticksPerOutClk-1 := 0;
begin
if( reset = '1' ) then
cycle_counter := 0;
elsif( rising_edge(clk_in) )then
cycle_counter := cycle_counter+2;
if( cycle_counter >= ticksPerOutClk ) then
cycle_counter := 0;
clkGen <= not clkGen;
end if;
end if;
end process;
end architecture Behavioral;
