Synthesis

[soathana]

I am trying to synthesize a circuit in ISE 13.2 using VHDL and Block memory generator

The problem is in Block RAMs.

I get multiple warnings on synthesis telling me that RAM is treated as a black box:

WARNING:Xst:2036 - Inserting OBUF on port <doutb<0>> driven by black box <ram_1_block>. Possible simulation mismatch.

I have looked into these 2 threads but with no luck...

http://forums.xilinx.com/t5/Archived-ISE-issues/How-to-use-custom-versions-of-Library-symbols-in-ISE...

http://forums.xilinx.com/t5/Synthesis/XST-Warning-Message/td-p/62089

The problem continues with errors of this type during design implementation:

NgdBuild:604 - logical block 'ram_all1s' with type 'ram_1_block' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'ram_1_block' is not supported in target 'virtex4'.

Please help, any ideas are welcome...

[hongh]

It's ok to treat the block ram as a black box. In translation, ise will combine the ngc of block ram together. 

Please confirm that the ngc file is in the working dir and check the instantiation code to see whether the port declaration is right.

[soathana]

ngc file is on my working directory,  and the instantiation code is right.

I still have no idea what's wrong ...

Could it be that somehow my project can not access the xilinxcorelib or something?

[hongh]

Could you show me the code you instatiating the block ram?

[soathana · Accepted solution]

Ok, i fixed it!!

Apparently i had forgotten to include some files in the project and now i don't get warnings neither on simulation nor in implementation steps.