I got rid of the rising_edge checks for Reset and Execute. I now just check their level...
Here's the code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity crcCalc is
Port (
clock : in STD_LOGIC; -- system clock (for shifting)
reset : in STD_LOGIC; -- reset signal (active high)
execute : in STD_LOGIC; -- Start calculation (active high)
data : in STD_LOGIC_VECTOR(31 downto 0); -- data for CRC
remainder: out STD_LOGIC_VECTOR(7 downto 0); -- result of CRC
idle : out STD_LOGIC -- Signals component state (idle = 1 available)
);
end crcCalc;
architecture Behavioral of crcCalc is
type crcStates is (IDLE_STATE, BUSY_STATE);
signal nextState : crcStates := IDLE_STATE;
-- Latch execute command so input doesn't have to be held high
signal executeCrc : boolean := false;
-- Registers to shift data during CRC calculation
signal crcShiftReg: std_logic_vector(7 downto 0) := (others=>'0');
signal dataIn : std_logic_vector(31 downto 0) := (others=>'0');
begin
process( clock, reset, execute )
variable crcCount : integer range 0 to 32 := 0;
begin
RST : if( reset = '1' )then
dataIn <= (others=>'0');
crcShiftReg <= (others=>'0');
nextState <= IDLE_STATE;
executeCrc <= false;
elsif( execute = '1' )then
executeCrc <= true;
else
case nextState is
-----------------------------------------------------------------------------
-- Pushes Idle output high, CRC calculation is available in Idle state
when IDLE_STATE =>
idle <= '1';
crcCount := 0;
if( executeCrc )then
dataIn <= data;
nextState <= BUSY_STATE;
end if;
-----------------------------------------------------------------------------
-- Locks out CRC component while performing calculation (unless reset).
when BUSY_STATE =>
idle <= '0';
if( crcCount < 32 )then
crcCount := crcCount + 1;
dataIn <= dataIn(30 downto 0) & '0';
crcShiftReg(0) <= dataIn(31) xor crcShiftReg(7);
crcShiftReg(1) <= crcShiftReg(0) xor crcShiftReg(7);
crcShiftReg(2) <= crcShiftReg(1) xor crcShiftReg(7);
crcShiftReg(3) <= crcShiftReg(2) xor crcShiftReg(7);
crcShiftReg(4) <= crcShiftReg(3);
crcShiftReg(5) <= crcShiftReg(4) xor crcShiftReg(7);
crcShiftReg(6) <= crcShiftReg(5);
crcShiftReg(7) <= crcShiftReg(6);
else
-- Calculation complete. Push out result and return to idle state
remainder <= crcShiftReg;
nextState <= IDLE_STATE;
executeCrc <= false;
end if;
end case;
end if RST;
end process;
end Behavioral;
