Debugging "WARNING:X
Hi everyone
I'm basically trying to write a state machine, which would simply give me a pulse at the second clock tick from start; the code is included below. In essence, it does simulate (below is post-par simulation):
... however, it generates the "WARNING:Xst:1426 - The value init of the FF/Latch ... hinder the constant cleaning" - and I'm not sure how to understand, or how to handle this warning. The machine has only three states - and I'm not sure if that may be the cause of the warning.
First of all, by calling in ISE:
- Behavioral simulation:
fusegets called on .prj file (which contains path to raw *.vhd source files); generates .exe file - Synthesize:
xstoperates on fsmContainer.prj (via fsmContainer.xst) and thus on vhd sources; generates .ngc (.ngr) binary netlist file
During the synthesis step, I get the following warnings:
Analyzing FSM for best encoding. Optimizing FSM on signal with one-hot encoding. ------------------- State | Encoding ------------------- sta | 001 stb | 010 stc | 100 ------------------- WARNING:Xst:1426 - The value init of the FF/Latch FFd3 hinder the constant cleaning in the block FSM. You should achieve better results by setting this init to 0. .... ========================================================================= * Low Level Synthesis * ================================================== ======================= WARNING:Xst:1426 - The value init of the FF/Latch FSM_FFd3 hinder the constant cleaning in the block FSM_0-parent. You should achieve better results by setting this init to 0. ...
Now the question is - what is this constant, whose "cleaning" is "hindered"? Since we cannot read directly the .ngc/.ngr files which are the output of .xst, only thing we can do is check the schematic: RTL schematic ("Launching RTL Schematic Viewer for fsmContainer.ngr"):
... and Technology schematic ("Launching Technology Schematic Viewer for fsmContainer.ngc"):
Interestingly, FFd3 exists only in RTL schematic (not in technology) - however, to see where this "init" comes from, we need to first convert the synthesis netlists back into (V)HDL. For that, the program "netgen" is used, which is called before any simulation step (other than behavioral) - and also, when you click:
- "Generate Post-Synthesis Simulation Model":
netgenoperates on fsmContainer.ngc, and generates ./netgen/synthesis/fsmContainer_synthesis.vhd file.
If we now open this fsmContainer_synthesis.vhd file, we can finally that this FFd3 does not exist there:
> grep FFd3 ./netgen/synthesis/fsmContainer_synthesis.vhd >
... (since that .vhd file actually corresponds to Technology Schematic). So we'd want to re-run netgen for the RTL netlist - however, netgen cannot run on .ngr files directly.
So we may want to try to directly generate "Post-Translate Simulation Model"... That calls:
- Translate:
ngdbuild- which creates .ngd file from .ngc - "Post-Translate Simulation Model":
netgen, which from .ngd file, generates ./netgen/translate/fsmContainer_translate.vhd
... and again no FFd3 to be found.
It seems that the .ngr is generated only with the purpose of viewing as RTL schematic - and it cannot be converted back into HDL. With that in mind, the only "constant" I can see (related to FFd3), is the ground going into FFd3.D on the RTL Schematic. If we could convert the .ngr back to VHDL, I'd bet we'd find something like this (which I got from other piece of code with a similar warning, modified):
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
state_fsm_FSM_FFd3 : FD
generic map(
INIT => '1'
)
port map (
C => clk_BUFGP_682,
D => N0,
Q => state_fsm_FSM_FFd3_657
);
... and the "INIT => '1'" would be the 'init' mentioned in the error message (it being different from the constant value of GND, applied to the D input).
Now, the thing is that no other warnings are generated for this code all the way to post-par simulation. So what should I think about "FSM_FFd3 hinder the constant cleaning" - should I try to "fix" it somehow or not? I could maybe try with an attribute INIT in an *.ucf file - however, that wouldn't do much good, as FFd3 exists nowhere other than the .ngr netlist, apparently.
The only other problem I can see, is that - in post-par simulation, if the OFFSET is less than 90 ns, then the pulse doesn't fire. Could that be related to the "FSM_FFd3 hinder the constant cleaning" warning?
I'd appreciate any guidance in how to think about this warning,
Cheers!
PS: The code:
-- file: fsm_tri.vhd
---------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- NEVER call port pins "in"; "out": ERROR:HDLCompiler:806 'Syntax error near "in"'!
ENTITY fsmContainer IS
PORT (
clk: IN STD_LOGIC;
p_out: OUT STD_LOGIC
);
END fsmContainer;
ARCHITECTURE structure OF fsmContainer IS
-- 'dummy signals' - registers
SIGNAL w_out : STD_LOGIC := 'Z';
-- fsm states
TYPE states_fsm IS -- ned: fsmContainer
(
stA,
stB, -- wait for in active low
stC -- signal for sampling
--,stD -- wait for in active hi
);
-- init fsm state vars
SIGNAL state_fsm, next_state_fsm: states_fsm := stA;
-- implementation:
BEGIN
-- assign 'wire' / registers
p_out <= w_out;
-- STATE MACHINES CODE =========
sm_fsm: PROCESS(state_fsm) -- combinatorial process part
BEGIN
CASE state_fsm IS
WHEN stA =>
next_state_fsm <= stB;
WHEN stB =>
next_state_fsm <= stC;
WHEN stC =>
next_state_fsm <= stC;
WHEN OTHERS =>
next_state_fsm <= stA;
-- WHEN stD =>
-- next_state_fsm <= stA;
END CASE;
END PROCESS sm_fsm;
out_sm_fsm: PROCESS(clk) -- synchronous process part --
BEGIN
IF (rising_edge(clk)) THEN -- returns only valid transitions;
IF state_fsm = stB THEN --
w_out <= '1';
ELSE
w_out <= '0';
END IF;
state_fsm <= next_state_fsm;
END IF;
END PROCESS out_sm_fsm;
-- END STATE MACHINES CODE =====
END structure; -- ARCHITECTURE
------------------
-- file: fsm_tri_twb.vhd
---------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY fsm_tri_twb IS
END fsm_tri_twb;
ARCHITECTURE testbench_arch OF fsm_tri_twb IS
COMPONENT fsmContainer
PORT(
clk: IN STD_LOGIC;
p_out: OUT STD_LOGIC
);
END COMPONENT;
-- 'wires'
SIGNAL wCLK : std_logic := '0';
SIGNAL wOUT : std_logic := 'Z';
-- clock parameters
constant PERIODN : natural := 20; -- can be real := 20.0;
constant PERIOD : time := PERIODN * 1 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 90 ns; -- at least 90 ?!
-- implementation of workbench
BEGIN
-- instances of components, and their wiring (port maps)...
UUT : fsmContainer -- VHDL
PORT MAP(
clk => wCLK,
p_out => wOUT
);
-- PROCESSES (STATE MACHINES) CODE =========
-- clock process for generating CLK
clocker: PROCESS
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
wCLK <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
wCLK <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS clocker;
-- END PROCESSES (STATE MACHINES) CODE =====
END testbench_arch; -- ARCHITECTURE
